Nuvoton Technology Corporation Japan

Takeshi Harada

Yoshihiro Matsushima

Shinya Oda

Yoshihiko Kawakami

Hiroaki Ohta

A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 μm; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 μm. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-μm square region located at least 13 μm inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Semiconductor device and chip singulation method

A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 &#x3bc;m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 &#x3bc;m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-&#x3bc;m square region located at least 13 &#x3bc;m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 &#x3bc;m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.

Growing community of inventors

Kagoshima, Japan

Takeshi Harada