Mitsubishi Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Renesas Technology Corp.

Nec Corporation

Nec Electronics Corporation

Zentel Japan Corporation

Sumco Corporation

Other

Nissan Motor Company Limited

Toshiba Memory Corporation

Takeshi Hamamoto

Kiyohiro Furutani

Mikio Asakura

Takashi Yamada

Akihiro Nitayama

Masaaki Mihara

Fumio Horiguchi

Takashi Kono

Katsuhiko Hieda

Takashi Kubo

Tadato Yamagata

Toshifumi Kobayashi

Takeo Miki

Masami Aoki

Yoshikazu Morooka

Shigehiro Kuge

Takuya Ariki

Takashi Ohsawa

Ryo Fukuda

Hajime Nagano

Katsuyoshi Mitsui

Masaru Haraguchi

Shigeru Kikuda

Yutaka Ishibashi

Tomoaki Shino

Zenya Kawaguchi

Takayuki Nishiyama

Hideaki Aochi

Masaki Tsukude

Yasuhiro Konishi

Tohru Ozaki

Yasuhiko Tsukikawa

Kenichi Yasuda

Tetsuya Nakai

Yoshihiro Minami

Satoshi Kawasaki

Hiroshi Watanabe

Kei Hamade

Hironori Iga

Bong-Gyun Ko

Keiichiro Tounai

Motoko Hara

Fujio Masuoka

Tsukasa Ooishi

Katsuya Okumura

Daisaburo Takashima

Yoshinori Tanaka

Masayuki Tanaka

Yoshitaka Tsunashima

Yukihito Oowaki

Akira Nishiyama

Tatsuya Kunikiyo

Hirofumi Inoue

Satoshi Inaba

Keisuke Nakatsuka

Seiji Sawada

Katsuhiko Hoya

Taku Ogura

Tadashi Miyakawa

Atsushi Murakoshi

Yasuhiko Taito

Takashi Yoshikawa

Hiroyuki Takenaka

Hidenori Mitani

Mitsuya Kinoshita

Shigeyoshi Watanabe

Yoshiaki Matsushita

Kazuya Matsuzawa

Tetsushi Tanizaki

Michihiro Yamada

Shigehiko Saida

Takanobu Suzuki

Kazumasa Sunouchi

Osamu Arisumi

Naoyuki Shigyo

Tomoya Kawagoe

Susumu Tanida

Hideyuki Ozaki

Masakazu Hirose

Kazumi Inoh

Makoto Yoshimi

Tetsuo Kato

Yasuhiro Matsumoto

Takahiro Kurosawa

Jun Setogawa

Mikio Nozaki

Kei Kurosawa

Nobuaki Yokoyama

Mamoru Terauchi

Hiroki Wada

Hitomi Kawaguchiya

Makoto Kitagawa

Shigekazu Aoki

Anna Hayashi

Tomoya Kamada

Satoshi Yodogawa

Youji Tonooka

A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.

Semiconductor memory device

A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.

Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor

A mounting structure for a power conversion device includes: a vehicle body component extending in a front-rear direction of a vehicle; a mounting component provided on the vehicle body component; a drive unit held by the vehicle body component via the mounting component; and a power conversion device attached to the mounting component. A stiffness of the mounting component is greater than a stiffness of the vehicle body component. The power conversion device is arranged between a front end and a rear end of the drive unit in a side view of the vehicle.

Mounting structure for power conversion device

A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.

Apparatus and method for chip identification and preventing malicious manipulation of physical addresses by incorporating a physical network with a logical network

An authenticated network in which a physical network including physical nodes with actual physical substances and a logical network including logical nodes without actual substances are uniquely linked to expand public ledger technology, which secures Peer-to-peer (P2P) type communication on a logical network, to a physical network, is provided. The authenticated network includes a private key uniquely linked to a public key. The private key is generated by a key generator and an identification device having physical substance and included in an identification core. The private key is regarded as a physical address of the identification core and is confined in the identification core. The public key is publicized as a logical address of a logical node. The logical node and the physical node are uniquely linked by the public key and the private key. The security of the whole network is thus effectively improved.

Authenticated network

According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

Magnetoresistive memory device

A memory includes first to fifth WLs extending in a first-direction. First to fourth element-regions extend in a tilt-direction. The first to fourth element-regions, respectively, intersect with the first and second WLs, with the third and fourth WLs, with the second and third WLs, and with the fourth and fifth WLs. A first connection-portion is arranged on an end of the first element-region and an end of the second element-region between the second and third WLs. A second connection-portion is arranged on an end of the third element-region and an end of the fourth element-region between the third and fourth WLs. First to fourth MTJs are, respectively, arranged above the first to fourth element-regions. The first and second MTJs are on a substantially same line along a second direction orthogonal to the first direction. The third and fourth MTJs are on a substantially same line along the second direction.

Semiconductor storage device

This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.

Semiconductor memory device and manufacturing method thereof

An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.

Semiconductor memory device including ferroelectric capacitor

This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Semiconductor device and method for manufacturing the same

To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide filmon the surface of a substrateconstituted of single crystal silicon, oxygen ionsare implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide filminside the substrate. Further included is a step of forming a predetermined-depth concave portiondeeper than substrate surfaceserving as a bulk area on which the mask oxide film is formed on the substrate surfaceserving as an SOI area by forming a thermally grown oxide filmon the substrate surfaceserving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Method of manufacturing SOI substrate

In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.

According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate below the contact plugs.

Method for manufacturing NAND-type semiconductor storage device

Growing community of inventors

Hyogo, Japan

Takeshi Hamamoto