Sony Corporation

Nippon Telegraph and Telephone Corporation

Takeshi Fukami

Akira Sakamoto

Takehiro Sugita

Masakatsu Toyoshima

Michimasa Komatsubara

Toshiro Terauchi

Yoichiro Sako

Tadao Suzuki

Akira Shimizu

Taro Nakagami

Shigeru Imura

Toshihiko Waku

Toshiya Miyata

Hisayoshi Sugiyama

Kohichi Suto

An error correcting apparatus including a circuit for detecting error correcting modes of incoming digital information, a generator for generating a first set of syndromes for a first error correcting mode when the incoming digital information is detected as the first error correcting mode, a generator for generating a second set of syndromes for a second error correcting mode when the incoming digital information is detected as the second error correcting mode, a generator for generating quasi-syndromes for the second error correcting mode by adding an additional syndrome to the syndromes for the first error correcting mode when the incoming digital information is detected as the first error correcting mode, and an error correction circuit for applying an error correcting process to the incoming digital information based on the generated syndromes for the second error correcting mode in spite of the error correcting modes of the incoming digital information.

Error correction processing apparatus

A synchronizing system for use with a plurality of digital signal reproducers includes a plurality of digital signal reproducers, each having a digital I/O modulator, a digital I/O demodulator and a decoder; a digital signal multiplexer supplied with the output signal from the plurality of digital signal reproducers, and for producing a frame synchronizing signal, a plural channel of digital signals; the digital signal multiplexer including a clock pulse generator, a word synchronizing signal generator, a digital I/O modulator and a digital I/O demodulator. The corresponding digital I/O modulator and digital I/O demodulator are coupled to each other so as to synchronize the plurality of digital signal reproducers.

Synchronizing system for digital apparatus

A digital signal transmitting system includes a plurality of digital signal reproducers, each outputting a digital data signal to be time-division multiplexed; a digital signal multiplexer supplied with a frame synchronizing signal, a service bit signal and the output digital signals from the reproducers and for producing a block data signal including the frame synchronizing signal, the service bit signal and a plurality of slot data bits arranged with the digital data signals, each one bit within a multiple-frame, in which the service bit signal is indicative of the transmission mode and the slot data associated with each of the plurality of digital data signals being transmitted.

Digital signal transmitting system

A scrambling system for an audio frequency signal is disclosed which employs a timebase-compressing and/or expanding system to measure the compressed and/or expanded amount of a segment time length caused in a transmission recording and reproducing system. In the scrambling system of the present invention, a marker signal is inserted into a portion between the adjoining segments and transmitted from an encoder side to a decoder side, while at the decoder side, this marker signal is detected, the synchronization is achieved by this marker signal along the compression and expansion of the segment length and the respective segments are rearranged to the original correct order. Thus, the connected portion between the segments can be made smooth so that it is possible to obtain the scrambling system for an audio frequency signal having high accuracy and high reliability.

Scrambling system for an audio frequency signal

A digital signal composing circuit includes a first selector for selecting a plurality of digital data, a second selector for selecting one of the digital data and a feedback signal, a control circuit for controlling the switching of the first and second selectors and an adding circuit for adding outputs of the first and second selectors and supplying the added output to the second selector as the feedback signal wherein the final output is derived from the adding circuit. Thus, without using any multiplier, the signal processing can be widely used in the digital signal processing such as digital volume, cross-fade, fade-in/-out, mixing, linear interpolation and the like.

Digital signal composing circuit for cross-fade signal processing

A scrambling system for an audio frequency signal in which an audio signal is divided into blocks, each block being formed of a plurality of frames, the plurality of frames are rearranged on a timebase in a predetermined order at every block so as to be encoded and the encoded signal is re-arranged on the timebase in an original order so as to be decoded, in which there are provided a first signal processing circuit for inserting a redundant portion into a portion between adjoining frames and timebase-compressing the frames in response to the redundant portions upon encoding, a control signal generating circuit for inserting a control signal other than an audio information into the redundant portions, a control signal detecting circuit for detecting the control signal upon decoding and a second signal processing circuit for removing the redundant portions in synchronism with the detected control signal and timebase-expanding the frames in response to the redundant portions. Therefore, even when the audio signal is transmitted through a system in a transmission path having a timebase fluctuation such as a transmission path of a VTR (video tape recorder) and the like the frequency band region of which is restricted, the signal waveform is not distorted and a noise is not mixed therein so that the scrambling communication having high quality and high reliability can be presented.

Scrambling system for audio frequency signals

A system for detecting a marker signal with a predetermined pattern inserted periodically in an information signal comprises a circuit which repetitively generates window signals and successively shifts the window signals in a step-wise fashion during a predetermined interval, a detecting circuit which employs the window signals to detect at least a portion of a marker signal in the information signal when at least the portion of the detected marker signal occurs during one of the window signals, a circuit which determines when the detected marker signal has the predetermined pattern to generate a net marker signal in response thereto, and a circuit responsive to the net marker signal which repetitively generates subsequent unshifted window signals beginning a predetermined time after the detected marker signal.

System for detecting a marker signal inserted in an information signal

A pulse width modulated signal amplifier includes an integrator having a positive or non-inverted input terminal supplied with a modulating signal, such as, an audio signal, and an inverted input terminal supplied with a rectangular wave signal as a carrier, a high gain amplifier receiving the output of the integrator and producing a pulse width modulated signal, a pulse power amplifier receiving the pulse width modulated signal, a low pass filter receiving the output of the pulse power amplifier and producing an amplified demodulated signal corresponding to the original modulating signal and which is supplied to an output terminal, and a negative feedback circuit connected between the output terminal of the pulse power amplifier and the inverted input terminal of the integrator.

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Tokyo, Japan

Takeshi Fukami