Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takeshi Fujino

Kazutami Arimoto

Hiroki Shimano

Fukashi Morishita

Takahiro Tsuruda

Mitsuya Kinoshita

Tetsushi Tanizaki

Mako Kobayashi

Teruhiko Amano

Hideyuki Noda

Akira Yamazaki

Takeshi Hashizume

Masaru Haraguchi

Katsumi Dosaka

Isamu Hayashi

Atsuo Mangyo

Koji Nii

Masaki Tsukude

Yasuhiko Taito

Naoya Watanabe

Makoto Hatakenaka

Kazunari Inoue

Yaichiro Watakabe

Koichi Moriizumi

Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to memory cell array blocks, respectively. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands in column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

Semiconductor memory device storing redundant replacement information with small occupation area

Column redundancy data storage circuit blocks storing column redundancy data for repairing defective columns are arranged in correspondence to respective memory cell array blocks. The storage data of the column redundancy data storage circuits is transferred to redundancy data hold circuits arranged in spare column decoder bands adjacent to the data paths for transferring internal data, and are decoded for selection of a page in the spare decoder bands during column access. Therefore, it is possible to reduce the occupation area of a fuse program circuit which programs redundancy data for repairing a defective column.

When to a memory cell arraya read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory unitstoeach of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory unitsto, respectively. In the 7-bit data, the written bit data has an interval of four bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.

Memory circuit

In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

Refresh-free dynamic semiconductor memory device

In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.

Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip

A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.

Semiconductor integrated circuit device with test data output nodes for parallel test results output

A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

Low-power consumption semiconductor memory device

A DRAM includes a sense amplifier which is activated when first and second nodes are set respectively to L and H levels to amplify a potential difference between paired bit lines. The DRAM further includes a write column select gate which is activated when the first node is set to L level to write a data signal on a pair of write data lines into a corresponding sense amplifier when a corresponding write column select line is set to H level. In this way, the data signal can be written into the sense amplifier simultaneously with sensing and amplification of memory cell data, which can enhance the random access rate.

Semiconductor memory device having write column select gate

Logic-merged memory

This DRAM includes a driver circuit which is provided to be common to a plurality of columns and which lowers level of one of selected first and second bit lines to &ldquo;L&rdquo; level in accordance with potentials of first and second write data lines. Therefore, as compared with a conventional DRAM in which a driver circuit is provided for each column, the number of transistors is decreased and a layout area is reduced.

A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA . Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve

A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

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Hyogo, Japan

Takeshi Fujino