Mitsubishi Denki Kabushiki Kaisha

Fujitsu Ten Limited

Other

Mitsubishi Electric Semiconductor Software Co., Ltd

Takeshi Fujii

Tomohisa Koseki

Fumihiko Fujimoto

Yasuhiro Ami

Osamu Yamanaka

Kouichi Ogawa

Yasufumi Morimoto

Koyo Kegasa

Takayuki Umemoto

Takafumi Murai

Susumu Yamamoto

A disk reproducing apparatus with improved quality is provided which has a clamper and a clamper plate. By providing the clamp plate with connection portions radially extending from a radially inner peripheral portion toward radially outer peripheral portion of the clamp plate, the axial displacement relative to a clamp holder can be increased as compared to that in the existing structure. Moreover, by disposing the clamper on the radially inner peripheral portion of the clamp plate so as to be elastically deformable, the spacing in clamping can be increased to a drive part.

Disk reproducing apparatus

A variable valve control apparatus includes a variable valve timing mechanism that adjusts an actuation timing of an intake valve and an actuation timing of an exhaust valve; a variable working angle mechanism that adjusts a working angle of the intake valve; a variable valve control section that controls at least one of the variable valve timing mechanism and the variable working angle mechanism based on an engine load; and a negative pressure suppression control section. The negative pressure suppression control section suppresses a negative pressure of an inside of a cylinder when the negative pressure suppression control section determines that both of the intake valve and the exhaust valve close after an intake top dead center, based on opening conditions of the intake valve and the exhaust valve.

Variable valve control apparatus

A ring oscillator clock frequency measuring circuit includes a reference clock count timer and a ring oscillator clock count timer. The reference clock count timer starts its counting of a reference clock signal in response to a start instruction fed from a CPU, and outputs an overflow signal when its counting reaches a preset value. The ring oscillator clock count timer starts its counting of pulses of a ring oscillator clock signal in response to the start instruction fed from the CPU, and continues its counting until the reference clock count timer generates the overflow signal. The frequency of the ring oscillator clock signal is obtained from the count value of the ring oscillator clock count timer. This makes it possible to measure the frequency of the ring oscillator clock signal at high accuracy, and to reduce the current consumption by operating the CPU based on the ring oscillator clock signal after the measurement.

Ring oscillator clock frequency measuring method, ring oscillator clock frequency measuring circuit, and microcomputer

A divisible stocker capable of housing a plurality of CDs is arranged in an enclosure of an autochanger apparatus. A rack mounting a PU unit, which is a reproduction head of a CD is arranged between the stocker and an opening of the enclosure. Transfer means for transferring the CD between the opening and the stocker is also mounted on the rack. The rack is vertically movable. When reproducing a CD, selecting any of the CDs in the stocker at first, turning a feed screw in a state where a pawl of a dividing sliding member is positioned below any of dividing projections arranged at corresponding position on the both sides of the stocker, causing a PU unit to advance into a space formed by raising the stockers above the selected CD, dividing the same and causing an upward displacement thereof, attaching the CD on a turntable of the PU unit by lowering the divided stocker, and transferring the CD to the turntable by displacement means which causes the PU unit to return to the PLAY position.

Reproduction/recording apparatus having a divisible housing for disc-shaped recording carriers and a reproduction/recording head mounting rack

A microcomputer includes an analog-to-digital (AD) converter which converts analog data into digital data and then stores a plurality of data bits which represent the digital data, a read signal output unit for producing a read signal for identifying the value of the digital data stored in the AD converter, a gate circuit which, in response to the read signal from the read signal output unit, obtains a plurality of data bits at the uppermost or lowermost end of the digital data from the digital data stored in the AD converter, a skip circuit which, in response to the read signal, obtains remaining data bits, other than the plurality of data bits obtained by the gate unit, from the digital data stored in the AD converter and produces a control signal having a second value which differs according to the value of the remaining data bits and a data identifying unit which identifies the value of the digital data on the basis of the plurality of data bits supplied by the gate unit and by the control signal.

Microcomputer communicating analog-to-digital conversion results to

A divisible stocker, capable of housing a plurality of CDs, is arranged in an enclosure of an autochanger apparatus. A rack mounting a PU unit, which is a reproduction head of a CD, is arranged between the stocker and an opening of the enclosure. A transfer device for transferring the CD between the opening and the stocker is also mounted on the rack. The rack is vertically movable.

Reproduction/recording apparatus having a divisible housing for

In a vehicular-mount type autochanger apparatus, to avoid influence of external vibration, a chassis is supported in an enclosure in a floating state by a spring of a floating mechanism. A stocker capable of housing a plurality of CDs and a PU unit for playing back a CD are incorporated in the chassis. The PU unit is mounted on a rack which can be elevated and lowered. The rack is also mounted with transport means for transporting a CD that is inserted through an opening of the enclosure to the stocker side or transporting a CD in the opposite direction. A lock pawl can be projected from a rear end portion of the chassis. The lock pawl presses the chassis against the opening side and the floating state being established by the floating mechanism is thereby canceled. Thus, insertion and ejection of a CD can be performed in a reliable manner. As a result, the influence of external vibration can be avoided in performing reproduction or recording on a CD, and a CD can be inserted in a reliable manner.

Recording carrier reproduction/recording apparatus having a

A microcomputer includes an input terminal, coupled to the control terminal of a transmission gate, that receives a real-time request signal asserted by a peripheral. The transmission gate transfers data from a register to the peripheral in synchronism with the assertion of the real-time request signal so that data is provided to the peripheral in real time.

Microcomputer for outputting data to the outside of the microcomputer in

To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

Data transfer control apparatus wherein an externally set value is

Data transfer control apparatus wherein a time value is compared to a

A pulse width modulator comprises: a reload register (8) which stores data D1 set as an initial value of data D and loads to a waveform timer (3), every time one waveform cycle is counted; a comparing circuit (10) which compares the data D1 and data D2 when the data D1 is changed to the data D2; and an incrementer/decrementer (9) which functions as an increment when the data D2 is larger than the data D1 as the comparing result, and as an decrementer when smaller, and every time the one waveform cycle is counted by a cyclic timer (7), increments or decrements the data D1 held in the waveform timer (3); and changes the ratio of an 'H' level period and an 'L' level period of an output waveform relatively slowly, against the rate of change (from D1 to D2) of a set value D of a timer register (2) for setting the 'H' level period and the 'L' level period of a pulse width modulation waveform.

Pulse width modulator including incrementer/decrementer

An n-bit input count value is split into high-order n-1 bits and a low-order one bit so that the overflow signal 3a of the n-1 bit counter 2 for counting the high-order n-1 bits and the output signal 4a which is obtained by delaying the overflow signal 3a by half the cycle of the input clock by means of the delay circuit 4 are switched by the switch circuit 5 according to the low-order bit stored in the 1-bit register 6 to achieve a signal having a minimum decomposition width which is half the cycle of the input clock 7a.

Timer circuit

A PLL frequency synthesizer comprises a voltage controlled oscillator which oscillates in response to a frequency signal corresponding to a control signal to be input and which outputs the frequency signal as an output of said PLL frequency synthesizer; a multiplier means for multiplying a reference frequency signal to be input; a mixer for mixing the frequency signal which is output from the voltage controlled oscillator and the multiplied reference frequency signal which is output from the multiplier, and for outputting a frequency signal representative of a difference therebetween; a variable frequency divider for dividing the difference frequency signal at a variable dividing ratio; a fixed frequency divider for dividing the reference frequency signal at a predetermined dividing ratio; a frequency phase comparator for detecting a phase difference between an output signal from the variable frequency divider and an output signal from the fixed frequency divider and for outputting a phase difference signal therebetween; a filter for removing high frequency components of the phase difference signal which is supplied as the control signal to the voltage controlled oscillator; and a device for switching the polarity of the phase difference signal. An output frequency of the voltage controlled oscillator can be switched to either a frequency higher than or a frequency lower than the frequency which is H (H is a positive integer) times as high as the output frequency of the multiplier, or the output frequency of the voltage controlled oscillator can be switched to either a frequency higher than the frequency which is H times as high as the output frequency of the multiplier or a frequency lower than the frequency which is (H+1) times as high as the output frequency of the multiplier.

Growing community of inventors

Hyogo, Japan

Takeshi Fujii