Hitachi, Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Microcomputer Engineering, Ltd.

Takeshi Asai

Shigeki Morinaga

Junichi Tatezaki

Hisashi Kaziwara

Mitsuru Watabe

Norio Nakagawa

Hiroyuki Kida

Yugo Kashiwagi

Tetsuaki Nakamikawa

Masahisa Narita

Shunpei Kawasaki

Atsushi Hasegawa

Kozo Nakamura

Ikuya Kawasaki

Makoto Hanawa

Yasuyuki Kozima

Kazuhiko Iwasaki

Takuichiro Nakazawa

Yasushi Yokosuka

Kazuhiko Takaoka

Takao Yaginuma

Mamoru Ohba

Eiki Kondoh

Kagehiro Yamamoto

A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Multiplication, division and square root extraction apparatus

System for obtaining strict solution in accordance with accuracy of

The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.

Coprocessor executing pipeline control for executing protocols and

A high-speed image signal processing system for encoding an image signal, read out at a high speed, into an encoded signal, and/or for recording a decoded signal obtained through a decoding operation on an encoded signal. The image signal, obtained through a scanning operation on an original document, is sent to an encoder through an image bus. A code bus, provided at an output of the encoder, is connected with an encoded-signal memory for storing the encoded signal. A code transfer unit, for performing input/output operation over the encoded signal and for performing transfer of the encoded signal from the code bus to a system bus, is disposed between the code bus and the system bus. A control unit, performing control over the entire system, and a document management data memory, storing management data for performing management over documents stored in the encoded-signal memory, are connected to the system bus. Further, the control unit, when receiving a request from a data input/output unit, issues a command indicative of the start of the encoding/decoding operation to the encoder/decoder. The encoder/decoder, when receiving the command from the control unit, sequentially processes the data from the data input/output unit without any intervention of the control unit, and when the data processing is completed, informs the control unit of the end of the data processing.

High-speed image signal processing system

A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

System using microprocessor address lines for coprocessor selection

A function arithmetic unit which performs elementary operations at high speeds and which enables required memory capacity to be reduced. The function arithmetic unit includes a constant memory which stores a constant that corresponds to the number of successive iterative operations; a controller which causes addition or subtraction in the successive iterative operations; and arithmetic units which receive, as initial values, an argument of an elementary function value to be found and two constants determined depending upon the elementary functions to be found, and which subject these initial values to n iterative operations to produce elementary function values. A further arithmetic unit subjects the elementary function values to multiplication, addition, subtraction, or division, or a combination thereof, thereby to produce the thus obtained value.

Elementary function arithmetic unit

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Hitachi, Japan

Takeshi Asai