Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Takeshi Aikawa

Mitsuo Saito

Kenji Minagawa

Tatsunori Kanai

Tsukasa Matoba

Mitsuyoshi Okamura

Yoshinori Suzuki

Takeshi Saito

Toshimitsu Kaneko

Hiroshi Yao

Osamu Hori

Toru Kambayashi

Shigeru Oyanagi

Akio Mori

Toshihiro Morohoshi

Shigeyasu Natsubori

Takahiro Harashima

Ken-ichi Maeda

Yasushi Kawakura

Shigehiro Asano

Seiji Maeda

Kenichi Maeda

Kenji Takeda

Toshiki Kizu

Toru Imai

Mitsuru Kakimoto

Junji Mori

Takashi Suzuoka

Nobuyuki Ikumi

Takeshi Yokokawa

Akihiko Nakase

Masahide Ohhashi

Shinya Amano

According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.

Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium

A method and a system for displaying multimedia data including video data. A display of video data and related information are controlled according to a movement of a pointing selection marker, a type of related information, or a distribution of pointing selection possible regions over frames of video data. Linked related information can be displayed in synchronization with a progress of a display of the video data. Information indicating a presence/absence of pointing selection possible region for currently displayed video data can also be displayed. A useful information can be obtained by collecting a statistical information on the desired positions specified by the user's pointing selection inputs. Each frame of video data can be partitioned and related information can be provided in correspondence to partitioned parts of each frame.

Method and system for displaying multimedia data using pointing

A message transmission and page processing scheme for a hypermedia document processing system, in which the source information which contains a source server identifier for identifying a source server in the system, a source page identifier for identifying a source page in the system, a request page identifier for identifying the request page in the system, and a request target server identifier for identifying a request target server in the system, is transmitted from a client device to a server device either directly or through a relay server device. A prescribed processing according to the source information is then carried out at the server device. In a case of using the relay server device, the relay server device can counts a number of source information, or separate the source information from a request message transmitted from the client device, or generate the source information from the page message from the server device and the request message from the client device.

Message transmission scheme and page processing scheme for hypermedia

A continuous data server apparatus incorporating a plurality of buffer memory units for storing the continuous data read out by the data memory control units and to be given to the communication control unit, at least one buffer memory unit being provided dedicatedly for each combination of one data memory control unit group formed by at least one data memory control unit and one communication control unit group formed by at least one communication control unit. The apparatus may further incorporate a plurality of calculation units connected in series, where each calculation unit is connected between corresponding one data memory control unit group and at least one buffer memory unit, and carrying out a prescribed calculation processing. The continuous data can be arranged over a plurality of data memory control units in word units, such that the data memory control units read out the continuous data in block units, the buffer memory units store the continuous data in block units, and the communication control unit transfers the continuous data obtained by reading out data the buffer memory units sequentially in word units.

Continuous data server apparatus and data transfer scheme enabling

An electronic computer which uses different bus protocols to transfer information for processor-to-processor communication and for processor-to-peripheral communication. The electronic computer includes an address buffer translator which translates a virtual address to a physical address and produces a bus protocol specifying signal. A bus interface changes bus protocols in accordance with the bus protocol specifying signal in order to permit a transfer of a physical address and data on the bus. In another embodiment, when the data in a cache memory is changed, a dirty bit for the cache memory is set but a corresponding dirty bit in the address translation buffer is not changed until a copy-back operation from the cache memory to a main memory occurs. The dirty page bit of the address translation buffer is changed utilizing software.

Computer system which switches bus protocols and controls the writing of

A parallel processing type processor system with trap and stall control functions capable of operating without increasing the cycle time, such that the lowering of the clock frequency in the system can be prevented. In the system, the processor units are controlled such that when an exception is caused in an execution of at least one of the instructions supplied to the processor units concurrently, the processings of all of the instructions supplied to the processor units concurrently are aborted. In addition, the processings of the instructions supplied to the processor units concurrently are stalled when it is not possible to deny a possibility for an occurrence of an exception in the execution of the instructions supplied to the processor units concurrently.

Parallel processing type processor system with trap and stall control

An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.

Electronic computer which executes squash branching

The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering entries, each entry including a branching address, a branch target address, and an instruction position indicating a position of the predicted branch instruction in group of instructions to be executed concurrently, or an entry address indicating a position of each entry in the associative memory of the table. A correctness of the predicted branch instruction is checked by using actual branch target address and/or actual instruction position of actual branch instruction encountered in the actual execution of presently fetched instructions. When the predicted branch instruction is incorrect, instructions fetched at a next processing timing are invalidated and the entry in the table is rewritten.

Method and apparatus for branch prediction using branch prediction table

A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructions and a corresponding decision result are stored in the cache memory. The decision process is performed for several groups of the plural instructions read out from the main memory to the cache memory in order. Then, the plural instructions are respectively assigned to a corresponding operation unit according to the decision result, and are subsequently executed by the corresponding operation unit. As a result of this arrangement, the repeated decision process for the plural instructions is not necessary when they are later read out from the cache memory to the operation unit.

Computer for simultaneously executing instructions temporarily stored in

A computer having a main memory for storing a plurality of data, a cache memory for temporarily storing a portion of the plurality of data, a processor for accessing data stored in the cache memory and processing the data according to instructions. The processor has an access instruction combined with a preload instruction, and an access instruction only for accessing data, and includes indicator circuitry for indicating a preload condition to the cache memory when the processor accesses data from the cache memory according to the access instruction combined with the preload instruction. The cache memory preloads data to be accessed next by the processor from the main memory when the processor indicates the preload condition.

Computer with main memory and cache memory for employing array data

According to an assigning method and its apparatus having a resource use recording section for recording a use state of a resource necessary for executing given operations, a functional unit possession recording section for recording information representing an inexecution functional unit, and an operator information management section for storing an operation executable by each functional unit and a clock count necessary for executing the operation, in order to assign an operation selected from the operations (by the operation selection step) to an optimal functional unit, the use state of the resource is checked from the resource use recording section (with reference to the usable resource decision step), the operation executable functional unit is found from the operation unit possession recording section (by the operation assignable unit decision step). A clock count necessary for executing the operation in the executable functional unit is considered with reference to the operator information management section. The optimal functional unit to be assigned with the selected operation is selected and decided (finally by the functional unit selection step), thereby performing an effective operation assigning process.

Operation assignment method and apparatus therefor

A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.

Three dimensional graphic processing apparatus

A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.

Growing community of inventors

Tokyo, Japan

Takeshi Aikawa