Mitsubishi Denki Kabushiki Kaisha

Other

Renesas Technology Corp.

Takeru Matsuoka

Takashi Yamashita

Hiroki Takewaka

Noriaki Fujiki

Takao Kamoshima

Shoichi Fukui

Shigeru Harada

Kazuhiro Tsukamoto

Masayoshi Shirahata

Takeshi Kitani

Shigeki Sunada

Takeshi Masamitsu

A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.

Semiconductor device including copper interconnect line and bonding pad, and method of manufacturing the same

A method for manufacturing a semiconductor device wherein a contact hole formed in an interlayer insulating film on a semiconductor substrate is filled with a plug for electrically connecting an overlying conductor layer with an underlying conductor layer. The plug fills the contact hole, and comprised a tungsten film the upper end whereof is positioned below the upper surface of the interlayer insulating film, and a tungsten film which is filled on the tungsten film in the contact hole and the upper surface whereof is on substantially the same level as the upper surface of the interlayer insulating film.

Method for manufacturing a semiconductor device

A plurality of MOS type FET devices and are provided on a semiconductor substrate A lower interlayer insulating film is provided thereon. Each of through holes which extends from each of gate electrodes of the plural FET devices via source/drain regions and , is defined in the lower interlayer insulating film A local wiring is buried in the through hole to connect each gate electrode and the source/drain regions and . Further, an upper interlayer insulating film is provided on the local wiring and the lower interlayer insulating film Upper electrode layers are placed on the surface of the upper interlayer insulating film

Semiconductor device having S/D to S/D connection and isolation region between two semiconductor elements

A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.

Semiconductor-device fabrication method

To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH -based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH -based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH -based silicon oxide film. The SiH -based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.

Semiconductor device

There are described a semiconductor device having multilayer wiring and a method for manufacturing the semiconductor device, wherein an interconnection hole for interconnecting an upper wiring layer to a lower wiring layer is formed correctly, thereby improving the reliability of multilayer wiring. A lower silicon oxide film, an upper silicon oxide film, and a silicon nitride film to be interposed therebetween are formed on a spin-on-glass (SOG) film. Enlarged openings for interconnection holes are formed only within the upper silicon oxide film while the silicon nitride film is used as an etch stopper, thereby preventing extension of the enlarged openings to the SOG film.

Semiconductor device, and method of manufacturing the same

A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5&times;10 atms/cm -2&times;10 atms/cm .

Semiconductor device with multi-layer interconnection

A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.

Method and apparatus for manufacturing semiconductor device

A lower insulating film is formed so as to cover source/drain regions electrically connected to capacitors. Bit lines and upper insulating layers are formed on the lower insulating film. SCs opening to the lower insulating film are formed by an anisotropic etching process on process conditions for etching the upper insulating films at a high upper insulating film/lower insulating film selectivity. An insulating film of a quality equal to that of the lower insulating film is deposited so as to fill up the SCs and to cover the upper insulating film. The SCs is extended so as to open to the source/drain regions by an anisotropic etching process on process conditions for etching the lower insulating film at a high lower insulating film/silicon film selectivity.

DRAM storage node with insulating sidewalls

A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Method of manufacturing a semiconductive device with an enhanced junction breakdown strength

A semiconductor device includes a pad electrode and a main electrode layer of the pad electrode has a plan view shape of one selected from the group consisting of a near circle, a near ellipse, a near polygon with at least one internal angle larger than 90 degrees and a near polygon with at least one corner chamfered or rounded. The main electrode layer is connected to a lower electrode layer beneath the man electrode layer via a connection hole interposed therebetween and a lower protruding section is provided beneath the lower electrode layer. A stress buffer insulating partition and a stress buffer protruding section are more preferably provided at corners of the layers, connection hole and lower protruding section.

Growing community of inventors

Tokyo, Japan

Takeru Matsuoka