Hitachi, Ltd.

Takeo Uchiyama

Kazuhiro Akimoto

Katsumi Ogiue

Masato Iwabuchi

Masami Usami

A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Semiconductor memory system for use in logic LSI's

A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.

Growing community of inventors

Oume, Japan

Takeo Uchiyama