International Business Machines Corporation

Takeo Nakada

Nobuyuki Ohba

Nobuyuki Harada

Munehiro Fukuda

Takashi Matsumoto

Nobuaki Takahashi

Tadanobu Inoue

Noboru Kamijo

Toru Aihara

Nobuyuki Oba

Nobuyuki Ooba

Ikuo Sho

The present invention can be a method, system, and computer program product. One embodiment of the present invention provides a computer-implemented method for identifying an artificial object. The method includes receiving capacitance data which is obtained by measuring with at least one electrodes in a sensor at least one predefined surfaces of the artificial object placed against the sensor; converting each of the obtained capacitance data into an evaluation level in an evaluation system having more than two evaluation levels, to obtain a capacitance distribution on the surface of the artificial object; determining whether the obtained capacitance distribution matches a pre-registered capacitance distribution or one of pre-registered capacitance distributions; and if the determination result is positive, concluding the artificial object is identified. The method can further include identifying or performing an authentication of a user associated with the artificial object when artificial object is identified.

Identification of artificail object and artifical object used therein

A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory.

Technique and apparatus for identifying cache segments for caching data to be written to main memory

To ensure efficient access to a memory whose writing process is slow. There is provided a storage device for caching data read from a main memory and data to be written in the main memory, comprises a cache memory having a plurality of cache segments, one or more cache segments holding data matching with data in the main memory being set in a protected state to protect the cache segments from a rewrite state, an upper limit of a number of the one or more cache segments being a predetermined reference number; and a cache controller that, in accordance with a write cache miss, allocates a cache segment selected from those cache segments which are not in the protected state to cache write data and writes the write data in the selected cache segment.

System for caching data from a main memory with a plurality of cache states

A digital signal measuring apparatus comprises a bus probe unit for extracting a bus event occurring on a bus based on a digital bus signal on the bus of the system to be measured, a traffic measuring unit for counting the number of occurrences of bus event based on the occurrence information of the extracted bus event, and a console unit for acquiring and processing the count value of the traffic measuring unit.

Digital signal measuring apparatus and traffic observing method

A means for preserve cache consistency is provided for a system comprising a central processing unit, a first physical memory, a second physical memory for which the address is common to the first physical memory in at least some duplicated address range of the entire physical address, a cache memory, and a memory controller, wherein the first or second physical memory is selected depending on the operation mode. Flag bits are provided in a tag memory of the cache for information identifying the data source. The cache then does not determine a cache hit/miss only based on whether data related to a CPU requested address exists in the cache, but determines whether the source of data requested by the CPU is consistent with the source of data stored in the cache by taking into account information on the operation mode simultaneously sent from the CPU. A cache hit is determined only when such two conditions are met.

Preserving cache consistency in a computer system having a plurality of

Cache flush mechanism for a secondary cache memory

In a tightly coupled multiprocessor system, I/O interrupts are distributed to respective processors in accordance with load conditions of the processors without partiality to any one processor. Interrupt arbitration circuits provided in respective processors receive an interrupt request from an I/O device, effect interrupt arbitration using a parameter indicating the load condition of each processor as a first interrupt priority. If the arbitration fails to determine a sole processor, additional arbitration finally selects a sole processor P on the basis of the second interrupt priority which is varied circularly.

Multiprocessor system and interrupt arbiter thereof

A synchronization controller is provided for each processor in a multiprocessor system. The synchronization controllers are commonly connected to a synchronization signal bus. Each of the synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor, signal means for transmitting a synchronization wait signal to the synchronization signal bus, a synchronization register for specifying the other processors to be synchronized with the corresponding processor, a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization resister, and a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of comparison by the comparator means.

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Kawaguchi, Japan

Takeo Nakada