Mitsubishi Denki Kabushiki Kaisha

Mistubishi Denki Kabushiki Kaisha

Takeo Muragishi

Eiichi Arima

A thin film transistor is used as a load transistor in a memory cell in a SRAM. A load thin film transistor is arranged on an interlayer insulating layer on the surface of a silicon substrate. A silicon layer in which source/drain regions of the thin film transistor are formed is covered with an oxidation preventing film. An interlayer insulating layer which is to be subject to high temperature reflow processing is formed on the surface of the oxidation preventing film. The oxidation preventing film is formed of polycrystalline silicon, amorphous silicon, silicon nitride, or the like and formed on the silicon layer in the thin film transistor directly or through an insulating layer to cover the surface of the silicon layer.

Method of making semiconductor device having thin film transistor

Upward and downward variation of a threshold voltage of a TFT is effectively suppressed by a semiconductor device and a method of manufacturing the same. In the semiconductor device, a conductive layer is formed on the substantially same plane as a semiconductor layer forming a channel region and source/drain regions of the TFT, and is spaced from the semiconductor layer by a predetermined distance. A predetermined potential is applied to the conductive layer. Thereby, an electric field is applied from the conductive layer to the channel region of the TFT, so that variation of the threshold voltage of the TFT is effectively prevented.

Thin film transistor with means to prevent threshold variations

A p-well region is formed in a main surface of a semiconductor substrate. A contact electrode is electrically connected to a predetermined n-type impurity region formed in a surface of the p-well region. A diffusion preventing layer is formed between the contact electrode and a drain region of a TFT. An interconnection layer is formed on the semiconductor substrate with an interlayer insulating film therebetween. A diffusion preventing layer is also formed between the interconnection layer and a source region of the TFT. Diffusion preventing layers are further formed between a channel region of the TFT and the source/drain regions of the TFT.

Semiconductor device having thin film transistor with diffusion

A thin film transistor (TFT) capable of reducing the leakage current on the occasion when the transistor is OFF and lowering the resistance of an interconnection layer connected to source/drain regions and a method of manufacturing the same are disclosed. In the thin film transistor, the length in the channel width direction of a polycrystalline silicon film 15 in junction parts 15c of a pair of source/drain regions 15b and a channel region 15a is smaller than the length in the channel width direction of polycrystalline silicon film 15 in source/drain regions 15b. Accordingly, the leakage current generated in junction parts 15c on the occasion when the TFT is OFF is reduced. In addition, it is unnecessary to reduce the length in the channel width direction of source/drain regions 15b, so that the resistance of an interconnection layer connected to source/drain regions 15b is lowered as compared to the conventional one.

Thin film transistor and manufacturing method thereof

Semiconductor device having thin film transistor and method of

A method of making a non-volatile semiconductor memory device including a memory transistor of a dual gate structure in a memory cell adapted for storing memory information. A first gate insulating layer, a first electronically conductive layer and a second gate insulating layer are formed on the main surface of semiconductor substrate. An etching mask is formed on a third insulating layer formed on the semiconductor substrate. The third and second insulating layers are patterned by etching using a first etching technique while the conductive layer is patterned using a different etching technique to form a gate electrode narrower than the third insulating layer. Impurity ions are implanted diagonally into the main surface of the semiconductor substrate using the patterned third insulating layer at first gate electrode as masks.

Method of manufacturing MDS memory device having a LDD structure and a

Thin film transistor with reduced leakage current

A non-volatile semiconductor memory device includes a memory transistor of a dual gate structure in a memory cell adapted for storing memory information. The transistor includes a floating gate and a control gate insulated by an interlayer insulating layer having a laminated structure of silicon oxide and silicon nitride films. The nitride film of the interlayer insulating layer has a visor-like portion protruding from and overlying a portion of the lateral surface of the floating gate. The transistor further is comprised of impurity regions in a so-called LDD structure.

Growing community of inventors

Hyogo, Japan

Takeo Muragishi