Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Takeo Kondo

Kiyofumi Ochii

Masami Masuda

Fujio Masuoka

Makoto Segawa

Shoji Ariizumi

Isao Baba

Youichi Suzuki

Leiichi Yanagisawa

Kenji Kohguchi

This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Protected MOS transistor circuit

An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n.sup.+ -type layer diffusion formed in the p-type well region and connected between a gate of a C-MOS FET and ground. The n.sup.+ -type layer of the diode has a higher impurity concentration and a greater diffusion depth than those of n.sup.+ -type layers formed in the p-type well region and constitute the source and drain of an n-channel MOSFET.

Input protection device for C-MOS device

A semiconductor device comprises a semiconductor substrate of N conductivity, a semiconductor well of P conductivity type, a first semiconductor region of P conductivity type formed in the substrate, the first semiconductor region forming a source region or a drain region in a first MOS transistor of P channel type, a second semiconductor region of N conductivity type formed in the well, the second semiconductor region forming a source region or a drain region in a second MOS transistor of N channel type, and a third semiconductor region of P conductivity type for partially covering the peripheral and bottom surfaces of said second region, which are in the proximity of a boundary defined between the substrate and the well, the third semiconductor region having an impurity concentration higher than that of the well.

Semiconductor device

A positive feedback amplifier circuit for possible use with a semiconductor memory device includes first and second MOS transistors whose current paths are connected together between two power source terminals, the gate of the first MOS transistor being connected to a clock. A third MOS transistor has a current path connected between one of the power source terminals and the gate of the second MOS transistor and also has a gate connected to the junction between the first and second MOS transistors and to a resistive means whose other end is connected to one of the power source terminals.

Positive feedback amplifier circuitry

A method is provided by the present invention for manufacturing a semiconductor device which includes supplying an impurity for forming an impurity area in a semiconductor substrate wherein the amount of the impurity defining the corners of said area is adjusted so that the shape of said corners is controlled. In this method, adjustment of the amount of the impurity may be accomplished by supplying the impurity to said substrate by using a mask whose corners are enlarged or reduced for increasing or reducing the opening area of the mask. The adjustment of the amount of the impurity may alternatively be accomplished by supplying an impurity of conductivity type opposite to that of said impurity to the places where the corners are to be formed.

Semiconductor device with enlarged corners to provide enhanced punch

A semiconductor memory device includes a plurality of memory cells arranged in a matrix fashion, word lines each connected commonly to the memory cells arranged on the same row, plural pairs of data lines each pair connected commonly to the memory cells on the same column line, and a row decoder connected to the word lines. The semiconductor memory device further includes positive feedback amplifiers connected to the work lines, which respond to voltages on the word lines at a preset or higher level to pull up the potential on the word lines to a higher level.

Growing community of inventors

Yokosuka, Japan

Takeo Kondo