Nec Corporation

Fujitsu Corporation

Nhk Spring Co., Ltd.

Toshiba Storage Device Corporation

Japan Tobacco Inc.

Takeo Hayashi

Kenichi Myokan

Takayuki Sasaki

Hiroshi Ueno

Masao Hanya

Yoshiharu Kitamura

Satoshi Kamiya

Kentaro Sonoda

Tatsuhiko Nishida

Yoichi Hatano

Akihiro Motoki

Toshiki Watanabe

Tatsuya Kimura

Hitoshi Tambo

Daisuke Sumi

Masahiko Ebina

Hideo Kawai

Shigeru Kubo

Sumiko Yamamoto

Yoshiyuki Akita

A network management apparatus that connects to a terminal by way of a communication apparatus, includes: a legitimate information generation unit configured to generate legitimate identification information that is identification information to identify the terminal on a network that the network management apparatus manages, the legitimate identification information being managed as legitimate information by the network management apparatus; a fake information generation unit configured to generate fake identification information that is different from the legitimate identification information and that cannot be used as it is for communication with another terminal; a management unit configured to manage the legitimate identification information and the fake identification information in association with each other; and a registration unit configured to register the fake identification information to the terminal.

Network management apparatus, network management method, and recording medium

A semiconductor device including a multi-layer interconnection substrate having a signal distribution interconnection and a power supply line and semiconductor circuit blocks installed on the multi-layer interconnection substrate for performing required operations. The multi-layer substrate includes a third interconnection layer having interconnections extending in a first direction, a second interconnection layer having interconnections extending in a second direction which is different to the first direction, and a first interconnection layer having interconnections extends in a direction orthogonal to the first direction.

Configuration managing device for a reconfigurable circuit

A carriage for a disc device, which has a top arm, bottom arm, and mid arm, has a main mode, end arm mode, and mid arm mode as a frequency response obtained when subjected to a vertical shake. In the main mode, all of the top, bottom, and mid arms swing at a first frequency within the same phase in a primary bending mode. In an end arm mode, the top and bottom arms swing at a second frequency higher than the first frequency within opposite phases and with an amplitude larger than that of the mid arm. In the mid arm mode, the mid arm swings at a third frequency having a difference of 50 Hz or less from the second frequency within the same phase as in the main mode, and the top and bottom arms swing within the phase opposite from that in the main mode.

Carriage for disk device

A data processing device includes a memory, a processing unit, a logic element, a first database and a management unit. The memory stores a plurality of software modules which processes input data. The processing unit enables to execute the plurality of software module. The logic element enables to configure a plurality of hardware modules, which can perform processings equivalent to those performed by the plurality of software module, using a dynamic reconfiguration. The first database stores configuration information indicating a configuration of the plurality of hardware modules when the plurality of hardware modules is set to the logic element. The management unit determines a first software module to be set to the logic element as a hardware module in the plurality of software modules on the basis of a predetermined condition with respect to a processing of the input data, and sets a first hardware module corresponding to the first software module to the logic element with reference to the first database.

Data processing device and data processing method

An MFI synchronization manager determines the continuity of MFI values to manage the synchronization of the MFI values. A phase adjuster detects a reference VC-3 channel of VC-3 channels which make up a virtual concatenation based on detected MFI values. A write controller writes frame data into a phase adjustment memory based on a write permission signal from the phase adjuster and data valid/invalid information. A write frame manager manages the frame data written in the phase adjustment memory with respect to each of the VC-3 channels and generates a read permission signal for the frame data whose all VC-3 channels of the concatenation have been written. A read controller reads the frame data from phase adjustment memory according to the read permission signal.

Phase adjusting apparatus, phase adjusting method for use therein, and program for phase adjusting method

A data encoding apparatus extracts valid data to be encoded from received data and encodes the data, and realigns the encoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width. A data decoding apparatus extracts valid data to be decoded from received data and realigns the decoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width.

Data encoding apparatus, data decoding apparatus and data encoding/decoding system

A disk unit for reading information from or writing information to a disk by means of a head supported by an actuator includes a shroud having a face perpendicular to a surface of the disk and opposing a peripheral edge of the disk, and a spoiler having a given height in a direction perpendicular to the surface of the disk and extending above the surface of the disk from the peripheral edge generally toward a center of the disk.

Disk unit with increased head-positioning accuracy

A pipeline type processor, which is capable of determining a process starting address for each processor constituting the pipeline type processor prior to executing the process for increasing the processing capability of each processor even if the processing condition for each processor vary depending upon the type of ATM cell to be processed, is realized. Prior to cell process by a cell processing section, in which a plurality of processors are provided, an address determining section obtains key information such as the type of cell and the contents of the cell from the input ATM cell, and retrieves a process starting address for each processor by referring to a predetermined address storing table with the key information. The retrieved process starting address for each processor is transferred to the cell processing section, and each processor executes its process from the process starting address when the ATM cell has been stored into a buffer corresponding to own processor.

Pipeline type processor for asynchronous transfer mode (ATM) cells

A short leg brace which is composed of a foot mount and a calf splint pivotably attached to each other so as to allow plantar and dorsal flexions and which is provided with a compression spring between the splint and the heel portion of the mount for elastically hindering the plantar flexion.

Short leg brace

A disk drive includes a disk rotatably mounted in a housing, the disk having a plurality of tracks, a head for reading/writing data on the disk, and an actuator for moving the head across the tracks of the disk. The disk drive further includes a breathing filter fixed to the inner surface of a cover of the housing so as to close a breathing hole formed through the cover, and a breathing filter protecting member fixed to the outer surface of the cover so as to close the breathing hole and allow ventilation.

Growing community of inventors

Tokyo, Japan

Takeo Hayashi