Nec Corporation

Takenori Morikawa

Tsutomu Tashiro

Masaaki Soda

Satomi Shioiri

A clock identification and reproduction circuit which synchronizes a clock signal with an input signal includes a voltage controlled generator for generating a clock signal, a phase comparator for detecting a phase difference between an input signal and a clock signal to generate a phase difference signal according to the phase difference, and a filter for synchronizing a clock signal of the voltage controlled generator in response to a phase difference signal, in which the phase comparator generates a phase difference signal when a specific pulse waveform of a pulse of an input signal changes.

Clock identification and reproduction circuit

It is an object of the invention to provide a light-receiving module, in which alignments of optical axes of optical fibers and photodiodes can be easily carried out and efficiencies of light incidences on the photodiodes are not influenced by imperfections in a fabrication process. The light-receiving module according to the invention is composed of a photodiode-forming member and an optical fiber-supporting member. The photodiode-forming member is composed of light-receiving surfaces of the photodiode formed thereon and bank-shaped optical fiber-fixing guides for guiding the optical fibers along both their sides. The optical fiber-supporting member is composed of optical fiber-fixing grooves for fixing parts of the optical fibers near their output ends and reflector surfaces for changing directions of the lights emitted from light-emitting surfaces of the optical fibers. An attitude of the photodiode-forming member relative to the optical fiber-supporting member is so adjusted that the lights reflected by the reflector surfaces are precisely incident on the light-receiving surfaces of the photodiodes, and both the photodiode-forming and optical fiber-supporting members are stuck together.

Light-receiving module and method for fabricating a same

A parallel light receiving OEIC comprising a light receiving OEIC layed out in an array form, the light receiving OEIC having an optical fiber fixing groove, provided on a silicon substrate, for efficiently introducing light from an optical fiber into a photodiode, wherein at least one optical fiber fixing groove is provided between light receiving ICs for respective channels. This constitution enables the substantial distance between channels to be increased without increasing the layout area, resulting in reduced interference of noises generated in respective channels with each other, which markedly reduces the influence of crosstalk without increasing the layout area of the parallel light receiving IC.

IC for converting optical signal to electrical signal

There is provided an optical semiconductor device, including a first semiconductor layer, a first insulating layer formed on the first semiconductor layer, the first insulating layer having a different index of refraction from that of the first semiconductor layer, a highly doped, second semiconductor layer formed on the first insulating layer, a third semiconductor layer formed on the second semiconductor layer, a device isolation region having a depth starting at an upper surface of the third semiconductor layer and terminating at an upper surface of the first insulating layer, the device isolation region defining a device formation region therein, the device formation region being formed with a recess starting at an upper surface of the third semiconductor layer and terminating at an upper surface of the second semiconductor layer, a second insulating layer covering an inner sidewall of the recess therewith, a multi-layered structure formed within the recess, the multi-layered structure having at least a quantum well layer and a contact layer, a connection region having a depth starting at an upper surface of the third semiconductor layer and terminating at an upper surface of the second semiconductor layer, a first electrode formed on the connection region, a second electrode formed on the contact layer, and a light-impermeable region having a depth starting at an upper surface of the third semiconductor layer and terminating at an upper surface of the first insulating layer, the light-impermeable region being formed outside the recess. The optical semiconductor device can be fabricated in a planar structure, and has an improved photoelectric transfer efficiency. The optical semiconductor device makes it possible to integrate a light-emitting device and a light-receiving device on a common chip with the devices being optically insulated from each other.

SOI optical semiconductor device

Method of fabricating an optical semiconductor device

A photodetector design is disclosed for preventing an electrode from being broken. A recess portion is formed in a semiconductor substrate. A light absorbing layer is formed in the recess portion, and a buffer layer is formed on the light absorbing layer. A contact layer is formed on the buffer layer. The height of the light absorbing layer can be set to minimize the effect of a step caused by facet formation. An insulating layer is formed outside of a recess portion to project from a main surface of the substrate. The anode electrode is formed on the insulating layer and substantially outside of the recess and, as a result, the electrode is less likely to be broken.

Photodetector

A photodetector provides high photo-sensitivity, a low resistance of a cathode circuit and quick photoresponse, and includes a light absorption layer in a cavity, which is formed in a N-Si epitaxial layer and surrounded by a side wall oxide layer. A N-Si diffusion layer is formed on the bottom and the side wall around the cavity and has a lower resistance than the epitaxial layer. The diffusion layer contacts a cathode take-out region so that the resistance of the cathode circuit is decreased.

Photodetector and method for fabricating same

A photodetection semiconductor device is constructed in such a manner that a photodiode light absorbing layer includes an Si/SiGe super-lattice layer (6), which forms a layer in parallel with the surface of a silicon substrate (1), and upper and lower P type low Ge concentration SiGe epitaxial layers (5) and (7), which sandwich the Si/SiGe super-lattice layer between them and contain Ge lower than a Ge content in the Si/SiGe super-lattice layer, a highly dense P+ type Si contact layer (8) is directly formed on the upper SiGe epitaxial layer (7) and a highly dense N+ type epitaxial layer (2) is formed immediately below the lower SiGe epitaxial layer (5). Preferably, Ge concentration in each of the upper and lower SiGe epitaxial layers (5) and (7) is set to be at least 1% or higher.

Photodetection semiconductor device

SOI Optical semiconductor device

Disclosed is a semiconductor device, which is used as an optical detector and has: a photodiode section which has a first silicon layer, a light-absorbing layer and a second silicon layer which are in turn layered on a silicon substrate; wherein the light-absorbing layer is formed as a single silicon-germanium epitaxial layer and the single silicon-germanium epitaxial layer has a germanium concentration distribution which provides germanium concentrations of zero at its interfaces to the first silicon layer and the second silicon layer and provides a triangle-shaped concentration profile that a peak concentration value is provided in the middle of the single silicon-germanium epitaxial layer.

Semiconductor device having a GESC layer between silicon layers with

A semiconductor device with bipolar transistors formed in respective island regions in which collector regions of the bipolar transistors do not need to be pulled up to the top of the corresponding island regions and do not need to be contacted with a collector electrode on the top of the corresponding island regions. First and second semiconductor island regions are formed to be buried in a second insulator formed on a first insulator. First and second bipolar transistors are provided in the first and second island regions, respectively. An interconnection conductor for electrically interconnecting collector regions of the first and second transistors is formed in the second insulator and in contact with the collector regions of the first and second transistors. A common collector electrode formed on a third insulator covering the first and second island regions is electrically connected with the collector regions of the first and second transistors through the interconnection conductor, respectively.

Semiconductor device having bipolar transistors with commonly

A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar transistors, a capacitor formed on each of the first and second bipolar transistors, each capacitor including an insulating layer covering a surface of a respective one of the first and second bipolar transistors, a polysilicon layer formed on the insulating layer in a pattern that extends around the predetermined area, a dielectric film formed covering the polysilicon layer, and a conductive film covering the dielectric film.

Bipolar memory cell having capacitors

An alignment check pattern formed by a first insulating film; a first dummy pattern formed on a surface of said first insulating film; a second insulating film formed on a composite surface of said first insulating film and said first dummy pattern; a second dummy pattern formed on said second film, and positioned directly over said first dummy pattern in plan view; a third insulating film formed on a composite surface of said second insulating film and said second dummy pattern; a regular scale pattern formed on said third insulating film, and positioned directly over said second dummy pattern; fourth insulating film formed on a composite surface of said third insulating film and said regular scale pattern; and a vernier scale pattern formed on a surface of said fourth insulating film and positioned directly over said regular scale pattern.

Alignment check pattern for multi-level interconnection

A semiconductor integrated circuit device according to the present invention includes a semiconductor layer of a first conductivity type having a high concentration of impurity atoms which layer is formed in or on predetermined locations of a semiconductor substrate with the first conductivity type which locations requires a resistance to alpha rays. The device of the present invention can decrease the amount of the electron collection to a semiconductor layer of a second conductivity type having a high concentration of impurity atoms which layer is separated from the semiconductor layer of the first conductivity type having a high concentration of impurity atoms. Therefore, the semiconductor integrated circuit device of the present invention can have enhanced resistance to alpha rays without capacitances being increased and maintain a fast speed of circuit operation.

Growing community of inventors

Tokyo, Japan

Takenori Morikawa