Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takenobu Iwao

Nobuyuki Ikeda

Miho Yokota

Shuichi Kato

Takeshi Hashizume

Ryuichi Sakano

Yoshiaki Arima

A semiconductor integrated circuit includes a memory for holding data of a logic circuit inputs or outputs. The memory is composed of logic cells, and is placed in a logic region. Thus, the semiconductor integrated circuit can prevent forming wasted space, in which no circuit component is built, and reduce its area and power consumption. It can reduce the design period of the memory as compared with the case where hard macro cells are used.

Semiconductor integrated circuit and circuit design apparatus

A semiconductor integrated circuit device comprises vertical power supply wiring divided into first and second narrow-width vertical power supply wirings and , vertical ground wiring disposed in parallel with vertical power supply wiring and divided into first and second narrow-width vertical ground wirings and , auxiliary vertical power supply wiring connecting first narrow-width vertical power supply wiring and second narrow-width vertical power supply wiring , and auxiliary vertical ground wiring connecting first narrow-width vertical ground wiring and second narrow-width vertical ground wiring

Semiconductor wiring structure having divided power lines and ground lines on the same layer

There is provided a semiconductor integrated circuit device having a macro cell structure including: a rectangular macro cell region formed on a semiconductor substrate; a first diffusion region having the minimum permissible width, formed apart at least by a minimum inter-diffusion distance from both left and right side ends in upper and lower sides of the macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed. The first diffusion region is electrically connected with the second diffusion region.

Semiconductor integrated circuit device

A macro cell of field effect transistors includes source-drain areas respectively divided into a contact area and a non-contact area. One source-drain area of two of the source-drain areas located on opposite sides of the effective width portion of a gate electrode has a contact area at an upper portion and a non-contact area at a lower portion while the other source-drain area has the non-contact area at its upper portion and the contact area at its lower portion. The distance between effective width portions of gate electrodes where the non-contact area is located is smaller than the distance between effective width portions of gate electrodes where the contact area is located.

Macro cell

Connection between a PMOS transistor and an NMOS transistor is made through a refractory metal salicide layer in the source and drain regions of these transistors. The salicide is low in resistance, thereby partially substituting for a first Al wiring in intracell wiring. The resulting empty area provides a wiring area and, hence, the freedom of chip layout is enhanced. Besides, in a microcell which constitutes a logic circuit, such as a gate array, lateral wiring grid dots can be utilized as a wiring area.

Field effect transistor array including refractory metal silicide

A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.

Clock driver circuit and semiconductor integrated circuit device

A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected. The sixth common line is connected to clock signal supply lines which in turn are connected to a plurality of second macro cells.

Growing community of inventors

Tokyo, Japan

Takenobu Iwao