Nec Corporation

Nec Electronics Corporation

Takehito Inaba

Michihiko Ichinose

Kenji Oyachi

Shota Iwasaki

Hiromitsu Takeda

Atsuhiko Izumi

Kousuke Azuma

Ken Fukamachi

A circuit board including a base member, an interconnect layer formed on a part of the base member, an electrically-floating conductive layer formed on a substantially remaining part of the base member and having an edge adjacent to an edge of the interconnect layer, and a dielectric layer covering a part of the interconnect layer and an entire surface of the electrically-floating conductive layer and filling a gap between the edge of the interconnect layer and the edge of the electrically-floating conductive layer. In accordance with the present invention, almost all the surface of the base member is covered with the interconnect layer and the floating conductive layer disposed parallel to each other on a substantially single plane. In the circuit board, the moisture does not enter into the rear surface of the dielectric layer through the externally exposed portion to improve the packaging rank.

Circuit board

In a semiconductor device, semiconductor chips are mounted on two surfaces of a die pad. A lower one of the semiconductor chips has a portion projecting outward from an upper one of the semiconductor chips. The semiconductor chips are connected to integrally molded external connection leads trough wiring members. The lower semiconductor chipping the outwardly projecting portion has, on its surface on the same side as an upper surface of the upper semiconductor chip, pads to be connected to the external connection leads. A semiconductor device lead frame and a method of manufacturing the same are also disclosed.

Semiconductor device, and semiconductor device with die pad and protruding chip lead frame and method of manufacturing the same

A hybrid leadframe has first conductive leads extending into space over a semiconductor chip and second conductive leads outside the space, the first conductive leads and the second conductive leads are connected through bonding wires to bonding pads on the semiconductor chip, and the first conductive leads are directly adhered to insulating adhesive compound layers spread on predetermined area of the upper surface of the semiconductor device, wherein the second conductive leads are bifurcated so that one of the bifurcated portions is connected through the bonding wire to the bonding pad and the other bifurcated portion is adhered to the insulating adhesive compound layers so as to enhance the stability of the second conductive lead.

Hybrid leadframe having conductive leads less deformable and semiconductor device using the same

The resin-molded portion of a semiconductor package encapsulates a semiconductor element mounting portion, inner leads, and a heat dispersion plate. A semiconductor element is mounted on the surface of the semiconductor element mounting portion. The inner leads are arranged around the perimeter of the semiconductor element and are electrically connected to electrodes on the surface of the semiconductor element. The heat dispersion plate has legs, and the semiconductor element mounting portion is arranged to overlap with the heat dispersion plate. A bonding layer composed of thermoplastic resin, thermosetting resin, or low-melting metal is present at least between the heat dispersion plate and the semiconductor element mounting portion. A portion of the legs of the heat dispersion plate is exposed on the bottom surface of the resin-molded portion. Outer leads that are continuous with the inner leads extend outside the resin-molded portion.

Semiconductor package incorporating heat dispersion plate inside resin molding

Internal electrodes and external lead wiring lines are formed on the front surface of a substrate of a semiconductor device, and solder bumps electrically connected to the external lead wiring lines via through holes are provided on the rear surface of the substrate. A first semiconductor chip is mounted on the surface of the substrate, and a second semiconductor chip is mounted on the rear surface of the substrate. Electrodes of the first semiconductor chip are connected to bonding pads at one side ends of the internal wiring lines, and electrodes of the second semiconductor chip are connected to the bonding pads at the other ends of the internal wiring lines and the external lead wiring lines with bonding wires passing through openings provided in the substrate. The solder bumps are formed with a height equal to or greater than the thickness of the second semiconductor chip so that, when the semiconductor device is mounted on an external mounting board or the like, a gap is formed between the substrate of the semiconductor device and the external mounting board by the height of the solder bumps themselves. The second semiconductor chip mounted on the rear surface of the substrate is accommodated in the gap.

Semiconductor device with reduced thickness

In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Lead-on-chip type semiconductor device having thin plate and method for

A plastic-encapsulated semiconductor device is provided, which makes it possible to reinforce the power/ground line by a bus-bar without using the over-lead bonding technique. This device is comprised of (a) an IC chip having a surface on which a first plurality of bonding pads and a second plurality of bonding pads are provided, the first plurality of pads being arranged in a central area of the surface and the second plurality of pads being arranged in a peripheral area of the surface; (b) lead fingers whose inner ends are fixed to the surface of the chip, at least one of the fingers serving as a part of a power/ground line for the chip; (c) a bus-bar mechanically and electrically connected to the at least one of the fingers serving as a part of the power/ground line, the bus-bar extending over the surface of the chip and; (d) bonding wires for electrically connecting the inner ends of the fingers and the bus-bar to corresponding ones of the first and second pluralities of bonding pads; and (e) a plastic package for encapsulating the chip, inner portions of the fingers, the bus-bar, and the wires, while protruding outer portions of the fingers. The bus-bar extends over the central area of the surface of the chip so that the wires electrically connecting the first plurality of pads to corresponding ones of the lead fingers do not overlap with the bus-bar.

Plastic-encapsulated semiconductor device equipped with LOC package

There is provided a semiconductor device sealed therearound with resin, including (a) a lead frame formed with an island region and a plurality of inner leads, tip ends of the inner leads defining a cavity as viewed perpendicularly to a plane of the chip, the island region being located in the cavity, (b) a chip mounted on the island region of the lead frame and having a plurality of electrodes thereon, and (c) wires for connecting the electrodes of the chip to the inner leads. The cavity is defined so that a wire for connecting inner leads to electrodes located at corners on a diagonal line D1 of the chip is shortest in length and a wire for connecting one of electrodes located at a corner on a diagonal line D2 perpendicular to the diagonal line D1 is longest in length. The present invention makes it possible to shorten a wire which would receive greatest impact from molten resin in the step of introducing molten resin into a space defined by upper and lower molds and enclosing the semiconductor device therein. Hence, it is possible to prevent shortcircuits between adjacent wires in the above mentioned step, thereby providing a resin-sealed type semiconductor device with high yield and high reliability.

Resin-sealed type semiconductor device

A molding die for sealing a semiconductor element with a resin includes an upper and a lower mold half. A leadframe having a resin passage aperture is sandwiched between the lower mold half and the upper mold half. The lower mold half has a lower runner space, a lower cavity, and a lower gate provided between the lower runner space and the lower cavity. The upper mold half has an upper resin well, an upper cavity, and an upper gate provided between the resin well and the upper cavity. The length of the upper resin well in the direction of the flow of resin is equal to or greater than the distance from the lower gate to the front edge of a lower runner rising slope, to thereby obtain a final product which is free from resin burrs formed in the upper resin well.

Growing community of inventors

Tokyo, Japan

Takehito Inaba