Fujitsu Corporation

Fujitsu Semiconductor Limited

Spansion Llc.

Fujitsu Vlsi Limited

Takehito Doi

Tetsu Tanizawa

Shigenori Ichinose

Koji Takekawa

Masayuki Yonekawa

Hideo Tokuda

Takashi Matsumoto

Shinji Saito

Takehiro Akiyama

Yoshihiro Nagaya

Tsuyoshi Moribe

Kouzi Takekawa

Susumu Kato

Katsuya Shimomura

Satoshi Katayama

Yukinori Maekawa

Hidetaka Yamaura

Katuzi Hirochi

Kiyoshi Matsuo

Keita Sekine

A power control circuit includes a control circuit configured to perform a soft start operation before a power supply device performs a normal operation. The power control circuit also includes a counter circuit configured to divide a switching frequency of the power supply device in the normal operation, wherein the counter circuit measures a period of the soft start operation and when the period lasts for a set length, starts to divide the switching frequency, and wherein the power control circuit causes a comparator comprising the counter circuit to compare the frequency obtained by dividing the switching frequency with a reference frequency and corrects the switching frequency.

Power control circuit performing soft start operation. power supply device, and electronic device

A circuit with variation correction function is capable of obtaining an output characteristic near a desired value by suppressing variation of the output characteristic regardless of manufacturing characteristic variations of a component. An output signal different in phase from a reference signal is obtained by a dummy circuit having a capacitor of a same structure as a correction object capacitor in an operation circuit. The difference in phase between the reference signal and the output signal reflects manufacturing characteristic variation of the correction object capacitor. The difference in phase is detected by a phase comparator circuit and control signals are created by a control signal conversion circuit. Switches in the operation circuit are changed over with the control signal to adjust the capacitance of the correction object capacitor. The correction object capacitor is actuated at a capacitance near design capacitance regardless of manufacturing characteristic variation of the correction object capacitor.

Circuit with variation correction function

A DC-DC converter for converting an input voltage and generating an output voltage. The DC-DC converter includes an adjustment resistor. A control circuit generates a control signal and includes an external terminal to which the adjustment resistor is externally connected. A switching transistor is connected to the control circuit and turned on or off in accordance with the control signal. The control circuit includes an oscillator that generates an oscillation signal. The control circuit generates the control signal based on the oscillation signal and a signal that is in accordance with an output voltage or output current of the DC-DC converter. The oscillator monitors a first amount of current flowing through the external terminal of the control circuit and generates the oscillation signal in a cycle that is accordance with the monitoring result.

DC-DC converter with oscillator and monitoring function

A circuit for detecting a difference in capacitance between a first capacitor and a second capacitor provided in a sensor includes an oscillator configured to generate an oscillating signal, a phase comparator coupled to the oscillator to output a signal responsive to a phase difference between the oscillating signal delayed by the first capacitor and the oscillating signal delayed by the second capacitor, an integration circuit coupled to the phase comparator to output an integrated signal made by integrating the signal responsive to the phase difference over a time period equal to a predetermined number of cycles of the oscillating signal, and a sample-and-hold circuit coupled to the integration circuit to output a signal made by sampling and holding the integrated signal at substantially an end of the time period.

Circuit for detecting difference in capacitance

A voltage controlled oscillator having a wide oscillation frequency band, desirable carrier-noise characteristic, and desirable linearity of the oscillation frequency relative to a control voltage. The voltage controlled oscillator includes an oscillation unit and a control unit. The oscillation unit generates an output signal having an oscillation frequency corresponding to the control voltage in one of a plurality of oscillation frequency bands. The oscillation unit includes a switching unit for selecting one of the plurality of oscillation frequency bands in accordance with a switching signal. The control unit generates the switching signal in accordance with the control voltage.

PLL circuit including a voltage controlled oscillator and a method for controlling a voltage controlled oscillator

A PLL frequency synthesizer including a lock detection circuit which detects whether or not the PLL is locked. First and second phase difference signals are generated from a reference signal and a compared signal by a phase comparator. The lock detection circuit determines the locked condition and generates a clock detection signal using only the first and second phase difference signals and does not require an external clock signal. The lock detection signal is generated independently of the frequencies of the reference signal and the compared signal.

PLL frequency synthesizer with lock detection circuit

A PLL frequency synthesizer, which comprises a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit operated based on the first and second phase difference signals, and having an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively. At least one of the first and second bipolar transistors is an emitter-follower type. In another embodiment, a node is provided between two switches formed by CMOS transistors, to serve as an output terminal of the charge-pump circuit. In a further embodiment, two PMOS transistors are provided as switches, and a node is provided therebetween to serve as an output terminal of the charge-pump circuit.

Charge pump circuits for PLL frequency synthesizer

A signal level converter is disclosed, for converting a signal having a first logic voltage swing characteristic to a signal having a second voltage swing characteristic. The converter comprises a level converting section and a differential circuit coupled thereto. The level converting section converts the supplied signal at the first logic voltage swing to an intermediate signal at a logic voltage swing different from the first voltage swing. The differential circuit 3, being supplied with the intermediate signal, produces an output signal at the second voltage swing level that corresponds to the potential difference between a high and low potential power supplies.

ECL-to-CMOS signal level converter

A semiconductor integrated circuit includes a substrate which has a predetermined width in a first direction and a predetermined length in a second direction which is approximately perpendicular to the first direction, a plurality of cells which are provided on the substrate and are grouped into a plurality of generally rectangular unit blocks, where each of the unit blocks are made up of cells having mutually different widths in the first direction but a common length in the second direction, first interconnections for supplying at least one power source voltage to the cells, where the first interconnections are provided independently for each unit block so as to supply the power source voltage in common to each of the cells making up the unit block, a row of first terminals of the cells, within each unit block, arranged in the first direction, a row of second terminals of the cells, within each unit block, arranged in the first direction an interconnection region at least including a region which is defined by the rows of the first and second terminals, and second interconnections which are provided within the interconnection region with respect to each unit block and connects the cells within the unit block.

Semiconductor integrated circuit having polycell structure and method of

A semiconductor integrated circuit comprises a plurality of first hierarchical units of logic devices each including a plurality of bipolar logic devices having a polycell structure. The bipolar logic devices have a first standardized size in a first direction and are arranged in a second direction for a second standardized size in each first hierarchical unit. Each of the first hierarchical units is defined by first and second main edges extending in the second direction for the second standardized size, and first and second side edges extending in the first direction for the first standardized size. Each of the first hierarchical units consumes a generally identical electric power and has a first power feed system extending in the second direction for the second standardized size for feeding the electric power to the bipolar logic devices therein. At least a part of the first hierarchical units are arranged in the first direction to form a plurality of second hierarchical units having respective lengths in the first direction wherein the first and second side edges are aligned in the first direction in each of the second hierarchical units. Further, the second hierarchical units are disposed such that there are at least two second hierarchical units having respective positions which are different in the second direction. Furthermore, there is provided a second power feed system extending in the first direction so as to cross the first power feed system for feeding the electric power thereto.

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Kasugai, Japan

Takehito Doi