Panasonic Corporation

Takehiro Yano

Shinichiro Kataoka

Daisuke Fukuda

Tetsu Nagano

A stepping motor drive device includes: a first pulse generation circuit that generates pulses at rising or falling edges of a first clock signal; a second pulse generation circuit that generates pulses at rising and falling edges of a second clock signal; a first mask circuit that outputs or masks the output of the first pulse generation circuit depending on whether the second clock signal is normal; a second mask circuit that outputs or masks the output of the second pulse generation circuit depending on whether the first clock signal is normal; a logic circuit that logically combines the outputs of the mask circuits; a step position control circuit that determines the step position of a motor according to the output of the logic circuit; and a motor drive section that supplies a current to the motor according to the output of the step position control circuit.

Stepping motor drive device

A semiconductor device of the present invention includes: a power input terminal; an internal power supply circuit that converts a voltage supplied from the outside to the power input terminal into a predetermined voltage; an analog circuit connected to an output side of the internal power supply circuit; an internal power output terminal connected to the output side of the internal power supply circuit; a logic circuit power input terminal; a logic circuit connected to the logic circuit power input terminal; and interterminal wiring connecting the internal power output terminal to the logic circuit power input terminal. The internal power supply circuit has a configuration of supplying power to the analog circuit and the logic circuit, and in a package assembly (finished product), a resting current in the logic circuit can be inspected without being influence by a consumption current in the analog circuit.

Semiconductor device and method for inspecting the same

There are provided upper and lower switching elementsU toW andU toW for energizing motor drive windingsU toW, a control circuitthat starts outputting a control signal for energization based on an energization instruction, pre-drive circuitsU toW andU toW for controlling ON/OFF of the upper and lower switching elements based on the control signal, and short circuit detection circuitsU toW for detecting short circuits in a nodebetween the upper and lower switching elements to higher-potential and lower-potential power sources based on the control signal and a voltage of the node. The short circuit detection circuits are controlled to detect a short circuit in the node to the lower-potential power source with all the upper switching elements turned ON and all the lower switching elements turned OFF and to detect a short circuit in the node to the higher-potential power source with all the upper switching elements turned OFF and all the lower switching elements turned ON, in a state where the motor drive windings are not energized. It is possible to prevent a situation in which a short circuit cannot be detected depending on a resistance component of a drive target.

Power supply system with function of short circuit detection

A semiconductor device includes a phase compensation circuitusing a MOS capacitor with a structure in which an insulating film is disposed between a gate electrode formed on a semiconductor substrate and a diffusion layer. The phase compensation circuit includes first and second MOS capacitors. A gate electrode terminal of the first MOS capacitor is connected equivalently to a diffusion layer terminal of the second MOS capacitor that is a terminal opposite to the gate electrode terminal. A potential difference generating elementthat generates a potential difference by allowing a current to flow therethrough is connected between a diffusion layer terminal of the first MOS capacitor and a gate electrode terminal of the second MOS capacitor. When the MOS capacitors having the voltage dependence are used, e.g., as a phase compensation circuit element of an operational amplifier, the MOS capacitance is not reduced, no matter the range of the input or output voltage of the operational amplifier, so that the phase margin will not reduced.

Growing community of inventors

Osaka, Japan

Takehiro Yano