Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Takehiro Kamada

Kenichiro Hayashi

Akira Kisoda

Takaya Hayashi

Yuji Nakai

Hiroyuki Senda

Kouya Watanabe

Takashi Kakemizu

In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit () detects a termination timing of a Viterbi code, a compulsion generation unit () generates a compulsion value so as to pass a specific path at the termination timing and timings before and after the termination timing, and the compulsion value is set on a traceback pointer (). Therefore, even when the decoding state of a code before termination is degraded, decoding of a next code can be carried out without being affected by the degradation, thereby improving error correcting capability.

Viterbi decoding apparatus and Viterbi decoding method

A reception apparatus for receiving an OFDM signal having a plurality of pilot carriers that transmit predetermined pilot signals at predetermined symbols. The reception apparatus transforms the received OFDM signal to a frequency-domain OFDM signal, determines channel responses corresponding to the transmitted pilot signals for each of the pilot carriers among a plurality of carriers constituting the frequency-domain OFDM signal, determines, based on channel responses corresponding to first, second and third pilot signals transmitted sequentially in a same carrier, a channel response at a symbol between the second pilot signal and the third pilot signal, compensates a waveform distortion in the frequency-domain OFDM signal according to the channel response at the symbol between the second pilot signal and the third pilot signal and outputs the results.

Reception apparatus and method, and channel response measurement apparatus for receiving an orthogonal frequency divisional multiplexing signal

In the Viterbi decoder for decoding a trellis-coded modulated signal of this invention, a path memory is constructed of a general RAM, whereby the circuit size and power consumption are reduced. A trace-back section traces back path select signals stored in a trace-back memory by a predetermined length. Using the number of a node through which a most likely path passes obtained by the tracing back and in accordance with a trellis diagram, a subset number generator section outputs coding bits relating to transition to the node concerned and a subset number. A selector section selectively outputs a noncoding bit relating to the transition to the node based on the subset number.

Viterbi decoder and Viterbi decoding method

The present invention provides an error correction circuit for receiving and decoding a trellis-encoded signal of a series of data Z , Z , . . . ,Z which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits X , X , . . . ,X of an input p-bit series of data X , X , . . . , X (where p&gE;2, q&gE;p, and p>t&gE;1), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit includes: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k&plus;1.

Error correction circuit and error correction method

In accordance with a rate detecting method for detecting a predetermined rate at which a received signal has been coded, the coded signal is decoded based on a first synchronizing signal having a frequency corresponding to a first rate such that a first decoded signal (ST ) is generated and then it is judged whether or not synchronization is determined for the first decoded signal (ST ). If the synchronization cannot be determined, there is generated only a second synchronizing signal having a frequency corresponding to a second rate having a difference between itself and a first rate which is smaller than a permissible value of the rate determined by the lower and upper values of the rate (ST , ST ).

Encoding rate detection method and encoding rate detection device

The path temporary storage unit stores path select signals outputted from the ACS means over a certain period of time. The partial trace back unit performs a partial trace back between the first time point and the second time point by using the path select signals stored in the path temporary storage unit , and detects a non-passing node through which surviving paths do not pass at the second time point. The conversion unit receives the signals from the partial trace back unit , and converts the path select signal corresponding to the non-passing node into a predetermined fixed value. This decreases the probability of occurrence of a signal transition in the path memory , thereby reducing power consumption.

Apparatus and method for viterbi decoding

The present invention provides an improved Viterbi decoder with a trace-back memory that requires a much less storage capacity required for signal decoding processing as compared with a commonly-used trace-back memory. Based on an input received code, an add-compare-select (ACS) circuit generates path select (PS) signals, and m generated PS signals per unit are written into a path storing means and are fed to a starting node number deciding circuit where the number m indicates a trace-back length. The starting node number deciding circuit finds from the m PS signals a trace-back starting node number for a PS signal preceding the m PS signals. PS signals are read out from the path storing means, trace-back processing starts from the starting node number found by the starting node number deciding circuit, and signal decoding processing is carried out. This eliminates the need for providing a state of performing provisional trace-back processing for finding a starting node number, thereby reducing the number of states necessary for the decoding of signals from four down to three. This reduces the storage capacity of memory required for storing PS signals and thereby achieves a considerable reduction of the circuit size.

Viterbi decoder and viterbi decoding method

Disposed in an integrated circuit is a test circuit having: a plurality of tristate buffers each for supplying, in a test mode, a charging current to a stray capacitance of a corresponding wire on a printed circuit board through a corresponding signal terminal of the integrated circuit; and a plurality of exclusive-OR gates each for supplying a logical signal having a pulse width indicative of a time interval between an input transition time and an output transition time of a corresponding tristate buffer. A difference in capacitance between a state where a signal terminal is being properly electrically connected to a wire on the printed circuit board and a state where the signal terminal is being improperly electrically connected thereto, is converted into a difference in pulse width of a logical signal, based on which a defective soldering of open failure in the signal terminal is detected.

Integrated circuit incorporating a test circuit

Provided with an integrated circuit are plural output pad circuits being connected to wires by way of an output pin. Each output pad circuit comprises an input section for taking in an external test signal; a generator, connected to an output of the input section, for generating a signal whose logic value is the same as the logic value of a signal from the input section; a controller for controlling the generator; and a measurement section for measuring the logic value of a signal from the generator. The controller controls the generator in order that a logic 1 signal and a logic 0 signal generated by the generator have different electric current levels in the test operation mode. If there occurs a short between a wire being connected to an output pad circuit that receives a logic 1 signal and a wire being connected to an output pad circuit that receives a logic 0 signal, then signals from these output pad circuits will have the logic value of one of the logic 1 signal and the logic 0 signal that has a higher electric current level than the other. On the other hand, in the normal operation mode, the generator generates both a logic 1 signal and a logic 0 signal at the same electric current level so as to balance the electric current level.

Output pad circuit for detecting short faults in integrated circuits

The invention discloses a boundary scan cell circuit for use in checking a wire, establishing a connection between the output pin of one IC and the input pin of the other IC, for stuck-at '0'/'1' faults. In an input boundary scan cell circuit in connection with the input pin, a third selector, in response to a control signal, selects one of a signal from a logic signal input terminal and an XOR from an arithmetic unit thereby outputting a signal thus selected. The output of the third selector is latched by a first flip-flop. The arithmetic unit performs the XOR addition of the output of the first flip-flop and the value of a logic signal from the logic signal input terminal. The result of the XOR addition is scanned-out at a scan signal output terminal. This reduces the number of shift operation cycles required for scan-out of the test result thereby shortening the time taken for testing. In an output boundary scan cell circuit, test data is automatically logic-inverted, so that no shift operation cycles necessary for scan-in of inverted test data are required. Therefore, this reduces the time taken for testing.

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Osaka, Japan

Takehiro Kamada