Kabushiki Kaisha Toshiba

Micron Technology Incorporated

Toshiba Corporation

Takehiro Hasegawa

Koji Sakui

Fujio Masuoka

Shigeyoshi Watanabe

Yukihito Oowaki

Shinichiro Shiratake

Akira Umezawa

Tsuneaki Fuse

Ryu Ogiwara

Akihiro Nitayama

Fumio Horiguchi

Tomoharu Tanaka

Fumitaka Arai

Takashi Mori

Mark Alan Helm

Yuan He

Seiichi Aritome

Chikara Kondo

Masaki Momodomi

Ryo Fukuda

Toshiki Seshita

Masako Yoshida

Ryo Mitani

Daisaburo Takashima

Hiroaki Nakano

Chang Hua Siau

Hiroshi Sukegawa

Katsuhiko Hieda

Koichi Kawai

Kiyofumi Ochii

Susumu Shuto

Mitsuo Saito

Kazumasa Sunouchi

Hitoshi Kuyama

Masayuki Koizumi

Atsushi Kameyama

Takuya Fujimoto

Daigo Toyama

Ken-ichi Maeda

Masaki Ichikawa

Raj K Bansal

Hyunui Lee

Tamio Saimen

Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.

Self timing training using majority decision mechanism

Memory devices and associated methods and systems are disclosed herein. A representative memory device includes a substrate and a memory controller electrically coupled to the substrate. The memory controller can include a first in/out (I/O) channel and a second I/O channel. The memory device can further include a plurality of first memories and second memories coupled to the substrate and arranged in a stack in which the first memories are interleaved between the second memories. The memory device can further include (i) a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller and (ii) a plurality of second wire bonds electrically coupling the second memories to the second I/O channel.

Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods

Apparatuses, systems, and methods for faster memory access regions. A memory array may have a first bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

Apparatuses including memory regions having different access speeds and methods for using the same

Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.

Methods and apparatuses with vertical strings of memory cells and support circuitry

Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

Apparatus, systems, and methods to operate a memory

A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate

A semiconductor device comprises a memory cell array and a source line driver. Each of the memory cells in the memory cell array has a floating gate cell transistor which stores data by accumulating charge in the floating gate and a select gate transistor whose drain is connected to the source of the cell transistor and whose source is connected to a source line. The source line driver is configured so as to drive the source line in a write operation at a potential between the substrate bias potential of the cell transistor and select gate transistor and the ground potential.

Nonvolatile semiconductor memory device with memory cells, each having an FG cell transistor and select gate transistor, and a method of writing data into the same

A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.

Semiconductor memory device including MOS transistors each having a floating gate and a control gate

A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same

A semiconductor chip includes a logic circuit unit, at least one memory macro unit having a redundant memory cell which recovers a defect cell, electrode pad rows being arranged around the outside of the logic circuit unit and the memory macro unit, and the least one fuse unit group storing addresses of the defect cell and being arranged in a region along any edge of the semiconductor chip, and on the outside of the logic circuit unit, the memory macro unit and the electrode pad rows. Here, the logic circuit unit, the memory macro unit, the electrode pad rows and the fuse unit group are positioned on a semiconductor chip surface.

Semiconductor chip with fuse unit

Growing community of inventors

Yokohama, Japan

Takehiro Hasegawa