Kabushiki Kaisha Toshiba

Takehiko Hojo

Kenichiro Mimoto

Kaoru Tokushige

Masaharu Wada

Koji Kohara

Motohiro Enkaku

Toshiyuki Kouchi

Tomohiro Kobayashi

Daichi Kaku

Tetsuya Amano

Takanori Yoshimatsu

Hideaki Yamauchi

Akikuni Sato

Yoshinori Sugisawa

According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.

Nonvolatile semiconductor storage

According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell and a third memory cell. The first memory cell forms a connection path used for storage of data. The second memory cell varies a connection place from a connection place of the connection path formed in the first memory cell, and stores data different from the data stored in the first memory cell is stored. The third memory cell varies a connection place from the connection place of the connection path formed in the second memory cell, and stores data same as the data stored in the first memory cell is stored.

Semiconductor storage device and ROM generator

A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.

Semiconductor integrated circuit having insulated gate field effect transistors

A semiconductor integrated circuit includes a main memory cell array, redundancy memory cell array, memory macro and repair information transferring circuit. A repair information analyzing circuit fetches repair information of transferred unit repair information therein, outputs the repair information to the memory macro having a redundancy repair mechanism and subjects the memory macro to a redundancy repair process by the redundancy repair mechanism of the memory macro in a case where memory identification information of the transferred unit repair information coincides with memory identification information stored in a nonvolatile memory element.

Semiconductor integrated circuit and redundancy method thereof

A semiconductor integrated circuit device includes a first fuse circuit, a second fuse circuit, and a control signal generating circuit which sends a first control signal and executes program such that the resistance value of the first fuse circuit becomes greater than the resistance value of the second fuse circuit, and sends a second control signal and executes reprogram such that the resistance value of the second fuse circuit becomes greater than the resistance value of the first fuse circuit.

Semiconductor integrated circuit device and redundancy method thereof

A storage device includes: a wiring including a first conductor with a first conductivity; and first, second and third contacts, each including a second conductor with a second conductivity and contacting the wiring. The storage device also includes: a write switching circuit controlling current for writing information that flows through the first contact, the wiring, and the second contact, and changing resistance values of the first contact to write information; and a read switching circuit controlling current for reading information that flows through the first contact, the wiring, and the third contact.

Storage device

A semiconductor integrated circuit device includes a first memory circuit which stores normal data, a second memory circuit which stores determination information used to determine whether a value of the normal data is changed or not, and a determination circuit which determines whether a value of the normal data is changed or not based on the determination information. The capacitance of a data storage node of the second memory circuit is larger than that of a data storage node of the first memory circuit.

Semiconductor integrated circuit device in which a measure to counter soft errors is taken

A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.

Semiconductor memory device and method of testing the device

A semiconductor device includes a relief-subject circuit, a relief circuit, and a plurality of fuse elements. The relief-subject circuit implements a predetermined function. The relief circuit is provided to relieve the relief-subject circuit in order to implement the predetermined function. The plurality of fuse elements are provided corresponding to the relief circuit in order to replace the relief-subject circuit with the relief circuit, thus storing information to specify the relief-subject circuit when this relief-subject circuit is replaced by the relief circuit.

Semiconductor device having relief circuit for relieving defective portion

A semiconductor integrated circuit includes a regular cell array, a spare cell array, first and second memory circuits, a determining circuit, a generating circuit and a selecting circuit. When the regular cell array contains a defective regular memory cell, the defective regular memory cell is replaced with a spare memory cell in the spare cell array. Each of the first memory circuits stores data indicating whether an associated spare memory cell is used or not. Any of the second memory circuits stores address data indicating the address of the defective regular memory cell. The determining circuit determines whether each of the spare memory cells is used or not, based on the data stored in an associated first memory circuit. The generating circuit generates predetermined data. The selecting circuit selects and outputs the data generated by the generating circuit or address data stored in each of the second memory circuits.

Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data

A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.

Semiconductor integrated circuit

A semiconductor device includes first to third functional areas parted each other by a boundary region on a semiconductor substrate. A memory block is formed in the first functional area and includes memory cells and a redundancy memory cell substituted for one memory cell. A functional circuit block is formed in the second functional area and connected with the memory block via an interconnection line. A program interconnection block is formed in the third functional area so that it does not overlap with the interconnection line and includes a program interconnection section which forms a program forming a signal path so that a defective memory cell is substituted by the redundancy memory cell. A data transfer section extends over from the program interconnection block to the memory block and transfers program information relevant to the program of the program interconnection section to the memory block.

Semiconductor device having a redundancy function

A semiconductor integrated circuit device has core circuits having rectangular shapes in plan view and power lines surronding the core circuit to connect the cores with an external power supply. The power lines are constructed in a plurality of interconnection layers and include interlayer connections so that they have overlapping parts. Interconnections between core circuits are commonly used so as to decrease interconnection area.

Semiconductor integrated circuit device

An I/O circuit is capable of achieving a reduction of power consumption by preventing leak current while performing the pull-down or pull-up operation. The I/O circuit of the present invention is constructed so that an I/O terminal 5 is pulled down or pulled up only when the I/O terminal 5 is in an open state or at the same potential as the pull-down or pull-up potential provided to the I/O terminal 5 when the high impedance state is input to the I/O terminal 5. The I/O circuit comprises an output circuit providing tri-state outputs, a switch circuit for the pull-up or pull-down operation, and an input circuit connected to the I/O terminal, the switch circuit and internal circuits of a device.

Input/output circuit and a method for controlling an input/output signal

In a first inter-layer insulator film above source/drain regions of basic cells constituting a gate array, first contact holes (joint contacts) are placed, so that wings (joint plates) electrically connected with the source/drain regions via plugs in those joint contacts is locally placed above the source/drain regions. Above the wings is formed a second inter-layer insulator film, above which is formed a first level interconnection which constitutes one of metal wiring layers. In the second inter-layer insulator film are formed second contact holes, so that a semi-custom ASIC is provided in which the wings and the first level interconnection are electrically interconnected via the plugs in those second contact holes. The first and second contact holes, first level interconnection, etc. are automatically designed by use of a computer based on a grid pattern in the basic cells. According to the present invention, the basic cells need not be re-designed even if a first pitch of a pattern of the first contact holes is different from a second pitch of a pattern of the second contact holes, thus easily enabling automatic customization. Without increasing the area of the source/drain regions in the basic cells, any pitch of the wiring layers can be selected, thus increasing the integration density without deteriorating the performance of MOS FETs at the same time as reducing time required for the customization.

Growing community of inventors

Yokohama, Japan

Takehiko Hojo