Nec Corporation

Nec Electronics Corporation

Takehiko Hamada

Masayuki Hamada

Hiroaki Ohkubo

Naoki Kasai

Takeo Matsuki

Masaaki Sugimoto

Tadashi Fukase

Mikio Tanaka

In a position detecting system and method, an electron beam is irradiated to a sample including a portion to be measured, and the electron beam is caused to move in relation to the portion to be measured in the sample. Furthermore, a voltage is applied to the sample which is scanned by the electron beam, and a current flowing in the sample because of the applied voltage, is detected. Thus, the position of the portion to be measured can be determined from a scanning start position of the electron beam and the position where the detected current changes.

Position detecting system and method

In failure analysis method of a semiconductor memory device, an absolute value of a position difference between two fail bits of a two-dimensional bit map is calculated while a histogram corresponding to the absolute value of the position difference is updated. The bit map indicates a map of fail bits and each fail bit corresponds to a fail memory cell. The above calculation is repeated to all combinations of two of the fail bits in the bit map. Then, an expectation function value is calculated for each of values from the histograms and the number of the fail bits. Finally, whether the fail bits has regularity or irregularity for each value is determined based on the calculated expectation function value for the value.

Failure analysis system of semiconductor memory device

The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device, in which a contact alignment mark ( A) is formed in an interlayer insulating film ( ), and a wiring alignment mark ( A) is formed above a gate alignment mark ( A) so that the size of the wiring alignment mark ( A) is slightly larger than the gate alignment mark ( A). At the same time, all the other alignment marks at the lower side are shielded by a shield film ( S). Opaque alignment mark and opaque shield film are formed to shield all the alignment marks at the lower side, whereby the alignment marks can be successively formed while stacked on one another.

Semiconductor substrate and method of manufacturing semiconductor device

In displaying positional information on a fail cell or the like after a test on a semiconductor memory with a memory tester, an address conversion section of PC converts, based on positional information obtained from the memory tester, one address array information to a plurality of types of address array information of a logical address and an capacity section address, and a display section displays the positional information based on the plurality of types of address array information. This enables the state of a fail cell to be easily understood, contributing to improved efficiency of fault analysis.

Device and method for outputting positional information for LSI cells and recording medium for positional information output program for LSI cells

A device for capacitor characteristic evaluation is provided, which enables measurement of the characteristic of a capacitor immediately after the completion of its formation processes, and which improves the fabrication yield. This device is comprised of (a) a conductive region formed on a semiconductor substrate; (b) an interlayer dielectric layer formed to cover the conductive layer; (c) a first electrode formed on the interlayer dielectric layer; (d) a second electrode formed on the interlayer dielectric layer to be apart from the first electrode; the second electrode being electrically connected to the first electrode through the conductive region; (e) a capacitor dielectric formed to cover the first and second electrodes; the capacitor dielectric being contacted with the first and second electrodes; (f) a third electrode formed on the capacitor dielectric to be opposite to the first electrode via the capacitor dielectric; (g) a fourth electrode formed on the capacitor dielectric to be apart from the third electrode to be opposite to the second electrode via the capacitor dielectric; (h) the first electrode, capacitor dielectric, and third electrode constitute a first capacitor and the second electrode, capacitor dielectric, and fourth electrode constitute a second capacitor; and (i) the third and fourth electrodes constitute a pair of measuring terminals.

Characteristic-evaluating storage capacitors

A contact alignment mark (18A) is provided in an interlayer insulating film (17), and a wiring alignment mark (19A) is formed above a gate alignment mark (15A) so that the size of the wiring alignment mark (19A) is slightly larger than the gate alignment mark (15A). At the same time, all the other alignment marks at the lower side are shielded by a shield film (19S). All the alignment marks at the lower side are shielded by the opaque alignment mark and the opaque shield film, whereby the alignment marks can be successively formed while stacked on one another.

In a semiconductor memory device, a plurality of straight word lines are arranged in parallel with each other, and a plurality of stepwise bit lines are arranged approximately perpendicular to the word lines. A plurality of memory cells of a one-transistor, one-capacitor type are connected between the word lines and the bit lines.

Highly integrated semiconductor device having stepwise bit lines

An intermediate insulation layer provided between a wiring of gate electrodes on a semiconductor substrate and a wiring formed in an upper layer includes a first interlayer insulation layer, a silicon rich oxide layer stacked on the first interlayer insulation layer and containing excessive silicon atom, and a second interlayer insulation layer stacked over the silicon rich oxide layer. Processes are provided for selectively performing dry etching for the insulation layers in order to simultaneously and easily form a self-aligned type contact hole on the diffusion layer position at the gap between oppositely arranged gate electrodes and a contact hole on the wiring of the predetermined gate electrode. In this manner, on the diffusion layer and the wiring of the gate electrode, the self-align contact hole and the contact hole are formed in the same process. This permits elimination of the need for margins in formation of the contact hole in the semiconductor device adapted for ultra-high packing density.

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Tokyo, Japan

Takehiko Hamada