Fujitsu Corporation

Takehiko Fujiyama

Takashi Kawabata

Hiroaki Kameyama

Kenzo Kobayashi

Toshiaki Usui

Toshihiro Yamanaka

Nobuyuki Kaneko

Kaname Yoshida

Yuichi Sato

Yuichi Terui

Tetsuya Yasui

Youichi Ashida

Masashi Murakumo

Naomasa Nishimura

Hiroshi Niimi

Ryoichi Dangi

Toshinori Shima

Masaharu Yamamoto

Wada Yoshiyuki

Seiji Matsuo

Ryouichi Dangi

Yuichi Satou

Yuuichi Terui

Norifumi Todogawa

An IP-data transmitting apparatus performs an error correction coding by classifying data into a layer indicative of the priority order of the data based on importance and vulnerability of information included in the data, and combining a plurality of data components into combination patterns. The number of the combination patterns is specified with respect to each layer with predetermined priority order.

IP-data transmitting apparatus and IP-data transmitting method

Disclosed is a communication system that transmits data through a transmission path between a transmission side apparatus and a reception side apparatus, wherein the transmission side apparatus comprises a coding apparatus that creates redundantly-coded data from original data; a transmitting apparatus that sends the coded data coded by the coding unit to the transmission path; and a coding rate determining apparatus that sets and controls a coding rate in the coding unit, wherein the reception side apparatus comprises a receiving apparatus that receives the coded data sent through the transmission path; a decoding apparatus that decodes the original data from the coded data received; and a loss rate estimating apparatus that measures the loss rate on the path of the coded data sent, and wherein the coding rate determining apparatus of the transmission side apparatus varies and controls the coding rate in the coding apparatus based on the loss rate obtained.

Data transferring method, and communication system and program applied with the method

A plurality of distribution devices accommodate one or more respective cameras. Respective picture monitors are connected to a plurality of receiving devices. The plurality of distribution devices and the plurality of receiving devices are connected by a transmission line. This transmission line is in a ring shape, and transmits picture data by a time division multiplex method. On receipt of a request related to picture display from a user terminal, a central device transmits an instruction to the plurality of distribution devices and to the plurality of receiving devices, according to a usage condition of the transmission line and the number of simultaneously distributed pictures. The plurality of distribution devices distribute picture data according to the instruction, and the plurality of receiving devices receive the picture data according to the instruction.

Picture distribution system and method thereof

A video telecommunication system having a plurality of cameras (video cameras) installed at remote locations and a monitor for monitoring the video, provided with a video information describing unit for sending a switch command for the camera to a video transmission apparatus, simultaneously sending character information describing the video information of the camera in accordance with the switch command, and having the video information and the character information displayed on the monitor, whereby it is possible to easily record, change, and correct character information on the place name etc. combined with the video information.

Video telecommunication system

A method and an apparatus for transmitting data in a linear-type or ring-type network structured by a plurality of nodes and both-way transmission lines each connecting between adjacent nodes includes that each node operates as a left TE, a right TE, or an IE. The left and right TEs prepare token packets each including a transmission right and packet trailers each including data packet storage area. The left TE transmits the packet trailers on a right direction line of the both-way transmission line.

Method and apparatus for transmitting data in a linear-type or ring-type network

An apparatus for reproducing a system clock provided with a reproducing unit for reproducing a first time reference clock T , a generating unit for generating a system clock Sck, a generating unit for generating a second time reference clock T , a synchronization control unit for minimizing, based on the clocks T and T , the deviation between these clocks, a first calculating unit for calculating a difference between counts of the clock T counted in a predetermined time interval, and a second calculating unit for calculating a difference between counts of the clock T counted in a predetermined time interval, the outputs of the calculation of the differences being input to the synchronization control unit to minimize the deviation between the clocks, whereby it becomes possible to reproduce high quality data even when switching channels from one node to another node when reproducing digital data from a plurality of sending side nodes at a receiving side node.

Method and apparatus for reproducing system clock in digital data transmission network

A plurality of image transmitting apparatuses are connected to the image transmitting side of a transmission line, a plurality of image receiving apparatuses are connected to the image receiving side of the transmission line, and a plurality of logical channels are set on the transmission line. A predetermined logical channel is fixedly allotted to each image receiving apparatus, and each image transmitting apparatus is provided with a function of transmitting an image to an image receiving apparatus through any logical channel. Each image transmitting apparatus transmits an image to a designated image receiving apparatus through a predetermined logical channel.

Image transmission method and image transmission system

In a video transmission system which transmits video data through an ATM network, the ATM network sets up fixed virtual connections between transmitters and a receiver. In the receiver, a connection control portion designates a desired one of the virtual connections and a header controller only extracts cells of the designated virtual connection.

Video transmission system

Video data is coded at either a minimum transfer rate or maximum transfer rate and stored in a storage unit as a video reply message. In a case where the video data has been coded at the minimum transfer rate and stored, the video reply message is transmitted upon being multiplexed with an audio reply message if the actual transfer rate agrees with the minimum transfer rate. If the two transfer rates are different, invalid bits conforming to the difference between the rates are generated and the invalid bits, the audio reply message and the video reply message are multiplexed and transmitted. In a case where the video data has been coded at the maximum transfer rate and stored, on the other hand, the video reply message is decoded when an incoming call arrives, the video data thus obtained is coded based upon the actual transfer rate, and the video reply message obtained by coding is multiplexed with the audio reply message and transmitted.

Image communication apparatus having automatic answering and recording

A coding system includes a first coding part, a second coding part, a switch selecting one of the first and second coding parts, a multiplexer generating a multiplexed signal from a coded signal input via the switch, and a buffer memory temporarily storing the multiplexed signal. The coding system includes a controller which generates an invalidation signal, a reset signal and the select signal when the controller is notified of the occurrence of an error and which outputs the invalidation signal, the reset signal and the select signal to the multiplexer, the buffer memory and the switch. The select signal causes the switch to select the second coding part instead of the first coding part. The invalidation signal invalidates the coded signal supplied from the first coding part to the multiplexer before the coded signal from the second coding part is input to the multiplexer via the switch. The reset signal causes the multiplexed signal stored in the buffer memory to be erased.

Coding system having data controlling mechanism activated when error is

A variable-length code decoding device includes a serial-to-parallel converter for converting serial data into parallel data for every N bits where N is an integer. The serial data includes consecutive data pieces having variable data lengths. A buffer stores the parallel data which is sequentially read out therefrom for every 2 N bits and which is shifted by N bits in a high-order-bit direction in response to a carry signal. A register stores a shifted number 'j' which is read out therefrom in response to a clock signal. The shifted number 'j' indicates the number of bits to be shifted. A barrel shifter receives the parallel data from the buffer memory and shifts, by the shifted number 'j', the parallel data in the high-order-bit direction so that N-bit parallel data having a starting bit which corresponds to an (j+1)th bit of the parallel data from a most significant bit thereof is output from the barrel shifter. A shifted number/carry signal generator generates, on the basis of a code length of effective data contained in the N-bit parallel data and the shifted number stored in the register, an updated shifted number and the carry signal. The shifted number stored in the register is updated by the updated shifted number.

Variable-length code decoding device

Video and audio multiplex transmission system

A data packing circuit, used in a variable length coder, for receiving code words including variable length codes and code length information of the variable length codes, and packing the variable length codes with no gaps into successive units of bits having predetermined length. The code word is shifted in a first direction by a number of bits equal to a shift number, and in parallel, the code word is shifted in a second direction opposite to the first direction by a number of bits equal to the difference between the predetermined length and the shift number, and zero is filled in each vacant bit which is generated by the above shift operations. The shift number is determined by accumulation of the code lengths by modulo-n addition, n being equal to the predetermined number, and a carry addition of the code lengths whether or not a carry occurs over the above predetermined length in the accumulated value. Logical sums of respective bits of the shifted result in the first direction and corresponding bits of the output of an intermediate date register are obtained. The intermediate data register latches the logical sums in every cycle of the code word when a carry is not detected in the above accumulation, and latches the shifted result in the second direction in every cycle of the code word when the carry is detected. The logical sums are latched as output data of the data packing circuit when the carry occurs.

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Kawasaki, Japan

Takehiko Fujiyama