Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Takefumi Yoshikawa

Toru Iwata

Tsuyoshi Ebuchi

Yutaka Terada

Hiroyuki Yamauchi

Yukio Arima

Shiro Dosho

Hironori Akamatsu

Shiro Sakiyama

Satoshi Takahashi

Masahiro Fukui

Takashi Hirata

Yoshihide Komatsu

Naoshi Yanagisawa

Masaomi Toyama

Keijiro Umehara

Ryoichi Suzuki

Makoto Miyake

Hisanori Yuki

A receiver circuit which can suppress a voltage amplitude appearing on a transmission line. The receiver circuit, coupled to a first and a second transmission lines which transmit information by using currents, includes a first and a second current sources, a first and a second conversion sections which convert currents which flow respectively therein to voltages, a first transistor whose source is coupled to the first current source and to the first transmission line, and whose drain is coupled to the first conversion section, and a second transistor whose source is coupled to the second current source and to the second transmission line, and whose drain is coupled to the second conversion section. The gate and the drain of the first transistor are respectively coupled to the drain and the gate of the second transistor.

Receiver circuit and data transmission system

A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Phase comparator and regulation circuit

In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Receiver circuit

A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.

Resynchronization circuit

The first data transmitting/receiving device according to the present invention includes: a serial-parallel conversion circuit for converting received first serial data to first parallel data; a data selection circuit for selecting any one of the first parallel data and externally-supplied second parallel data and outputting the selected data; and a parallel-serial conversion circuit for converting the first or second parallel data output from the data selection circuit to second serial data which is to be transmitted.

Data transmitting/receiving device

A circuit for detecting whether an intermittent clock waveform signal of 50 MHz is received or not includes an offset receiver, a charge pump, a capacitor and a hysteresis comparator. A circuit for detecting whether a random data waveform signal of 500 MHz is received or not includes an offset-less receiver, a transition counter, a delay circuit and an AND circuit. An OR circuit outputs as a signal detection signal a signal indicating the OR operation result of respective outputs of the hysteresis comparator and the AND circuit.

Signal detector

The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

Frequency modulation circuit

An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.

Input circuit and output circuit

A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

Clock recovery circuit

The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means () for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element () included in the first filtering means () for allowing a first current to flow in accordance with the first voltage; current generating means () for generating a second current at a given rate to the first current; second filtering means () for accepting, as an input, the second current and outputting a second voltage; and adding means () for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

The driver circuit of the present invention includes: a drive section for generating a differential signal according to an input signal and outputting the signal to an electric cable or an optical transceiver; and a control section receiving a selection signal based on which the drive section selects to drive the electric cable or the optical transceiver, an identification signal, and a data signal, for generating a signal based on the received signals and outputting the generated signal to the drive section. During a period indicated by the identification signal, the control section controls the drive section to put the output of the drive section in a high impedance state when the selection signal indicates selection of the electric cable, or output a predetermined differential signal, not putting the output in a high impedance state, when the selection signal indicates selection of the optical transceiver.

Driver circuit and data communication device

The present invention aims at providing a phase comparator and a clock recovery circuit suitable for applications that support data signals with high-speed bit rates in the order of one gigabit per second. Phase comparators receive frequency divided signals NHOLDH and NHOLDL generated from a data signal RD/NRD, respectively, and intermittently perform a phase comparison between a signal dDAT and a signal CLK. This increases the timing margin for the phase comparison and makes it possible to perform a phase comparison for high-speed bit rate signals. The provision of phase comparators that serve as clock recovery circuits makes it possible to handle data signals with high-speed bit rates in the order of one gigabit per second.

Growing community of inventors

Osaka, Japan

Takefumi Yoshikawa