Hitachi, Ltd.

Hitachi Medical Corporation

Takeaki Okabe

Isao Yoshida

Kouzou Sakamoto

Mineo Katsueda

Kazutoshi Ashikawa

Mitsuo Ito

Shikayuki Ochi

Masatomo Furumi

Shigeo Mikoshiba

Minoru Nagata

Tetsuo Iijima

Akihiko Kougami

Masahiro Eto

Masatoshi Kimura

Isamu Orita

Shigeo Ohtaka

Hidefumi Ito

Yoshio Sakai

Toshiaki Masuhara

Osamu Minato

Ryuichi Shinomura

Masatoshi Morikawa

Isao Shimizu

Kenji Kaneko

Wasao Takasugi

Terumi Sawase

Hideaki Kato

Toru Toyabe

Masaru Takeuchi

Toyomasa Koda

Yasuo Nagai

Kazuo Hoya

Koozoo Sakamoto

Kouichiro Satonaka

Hidefumi Itoh

Yukio Shirota

In a method for driving a display device, by which energy stored in a plurality of electrodes serving as a capacitive load is recovered through switches, current paths for charging said electrodes from a charge supplying source differ from current paths for discharging the electrodes for the energy recovery.

Driving method and apparatus for display device

A switching circuit has switching elements for passing-through or cutting-off signals of a positive pulse, which is a rectangular pulse rising from a low level and falling after having kept a high level for a certain time as a high voltage input signal, and a negative pulse, which is a rectangular pulse falling from a high level and rising after having kept a low level for a certain time, the switching circuit being applied to a capacitive load driving device.

Switching circuit and display device using the same

A semiconductor integrated circuit has a semiconductor output device (3) , a sensor (5) generating an electric signal (7) relevant to heat generation (6) of the output device (3) and a microprocessor unit MPU 2, inside a chip (1). The MPU (2) is constructed of a memory (20) and CPU (22). The electric signal (7) generated from the sensor (5) is processed by the CPU (22) in accordance with a stored program of the memory (20). Accordingly, the drivability of the semiconductor output device (3) can be set in an optimum state corresponding to changes in chip temperature including changes that are only momentary.

Semiconductor integrated circuit having semiconductor output device

A semiconductor integrated circuit device includes a high voltage circuit and a high-speed signal processing circuit on the same chip. The high-speed signal processing circuit is made to have a stacked construction thereby to reduce the power consumption. It is also surrounded by ground potential lines so that it may be prevented from being adversely affected by a high voltage used in the high voltage circuit. Each of the high voltage elements composing the high voltage circuit has its principal surface formed at its base and collector regions with guard ring layers of the same conduction types as the respective ones of the high voltage elements. The guard ring layers extend over the elements and the semiconductor body and have lower impurity concentrations than the respective ones of the elements.

Semiconductor integrated circuit device

An insulated gate semiconductor device contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Insulated gate semiconductor device with back-to-back diodes

A transmitter/receiver for suppling a pulse power to a transducer and receiving a signal from the transducer comprises a parallel connection of a first circuit including a first switch element connected in series with a power supply having one terminal thereof connected to a common potential point, a second circuit including a second switch element connected in series with a receiver having one end thereof connected to the common potential point, and a third circuit including the transducer having one end thereof connected to the common potential point.

Transmitter/receiver for ultrasonic diagnostic system

A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.

Method of fabricating semiconductor devices which include vertical

A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.

Method for fabricating vertical MOSFETs

An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.

Insulated gate type field effect semiconductor device and a circuit

A semiconductor integrated circuit device is provided to include a vertical type MOSFET and a gate protection element for the MOSFET. The vertical type MOSFET is made up of a silicon layer of n-type conductivity formed on an n.sup.+ -type silicon substrate, a base region of p-type conductivity formed in the surface of the silicon layer of n-type conductivity, an n.sup.+ -type source region provided in the base region, and a gate electrode formed on a portion of the base region through a gate insulating film. The silicon substrate serves as the drain. The gate protection element is formed of a polycrystalline silicon layer which is provided on the base region through an insulating film and includes at least one pn junction. By virtue of forming the gate protection element over the base region rather than directly over the substrate, a more stable operation is achieved.

DMOS With gate protection diode formed over base region

An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.

Insulated-gate semiconductor device

In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

Insulated gate field effect transistor with source field shield

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Tokyo, Japan

Takeaki Okabe