Megachips Corporation

Takeaki Komuro

Hiromu Hasegawa

Toshimitsu Tatsuka

Masato Yamada

Kazuhiro Saito

Nobuyuki Takasu

It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data.

Image coding apparatus

An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value.

Image processor for code amount control

The image processor includes a &#x2153; multiplier circuit that approximately multiplies an input value X by &#x2153;. The &#x2153; multiplier circuit includes a loop operation circuit that repeatedly perform a predetermined operation by loops, and a setting circuit that sets a required number of loops in the loop operation circuit. The loop operation circuit includes a register that receives an input of an input value, a bit shift circuit that performs bit shift by 2 bits to the right on a value output from the register, and an adder circuit that adds an input value and a value output from the bit shift circuit, and inputs the added value to the register.

Image processor

An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame. The controller includes a first processing unit that obtains a generated amount of code used for a first predetermined number of immediately preceding macroblocks, a second processing unit that obtains an allowable amount of code available for a third predetermined number of immediately subsequent macroblocks including a currently target macroblock, based on a target amount of code for not more than a second predetermined number of macroblocks less than a total number of macroblocks included in one frame, and the generated amount of code obtained by the first processing unit, a third processing unit that obtains an expected amount of code expected to be used for the third predetermined number of macroblocks, and a fourth processing unit that sets a quantization parameter of a currently target macroblock, based on the allowable amount of code obtained by the second processing unit and the expected amount of code obtained by the third processing unit.

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Osaka, Japan

Takeaki Komuro