Fujitsu Corporation

Spansion LLC.

Takayuki Yoneda

Satoshi Eto

Toshikazu Nakamura

Takaaki Suzuki

Masafumi Yamazaki

Ayako Sato

Toshiya Miyo

Katsuhiro Miki

Noriko Kawamura

Yasuhiko Tanuma

An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Semiconductor device

A non-volatile includes a memory cell array for storing data, a decryption circuit for decrypting data read from the memory cell array using a prescribed computing process, and a decryption control circuit for activating the decryption circuit according to an inputted decryption command during a read operation.

Non-volatile semiconductor memory that prevents unauthorized reading

A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern for the memory chip. A pattern selector selects, during the first test mode, the internal test pattern outputted from the pattern generator, selects, during a second test mode, an external test pattern supplied via a test terminal, and outputs the selected test pattern to the memory chip. The memory chip mounted in the package is tested by use of, in accordance with a mode selecting signal, either the internal test pattern in the first test mode, generated within the logic chip, or the external test pattern in the second test mode, supplied from the exterior.

A nonvolatile semiconductor memory device includes a memory cell array which includes nonvolatile memory cells, and a control circuit which responds to a first command by performing a first batch erasure with respect to a selected group of the memory cells, and responds to a second command by performing a second batch erasure with respect to the selected group of the memory cells, the first batch erasure including preprogramming, erasure, and over-erasure correction in this sequence, and the second batch erasure including over-erasure correction, preprogramming, erasure, and over-erasure correction in this sequence.

Nonvolatile semiconductor memory device capable of correcting over-erased memory cells

A nonvolatile semiconductor memory device includes a memory cell array, a control circuit which repeatedly perform an automatic erasure operation with respect to an entirety of the memory cell array, the automatic erasure operation including a preparatory write operation prior to an erasure operation and a following erasure operation, and a counter which counts how many times the automatic erasure operation is performed with respect to the entirety of the memory cell array, wherein the control circuit stops the automatic erasure operation in response to an event that the counter counts a desired number.

Growing community of inventors

Kawasaki, Japan

Takayuki Yoneda