Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Sharp Kabushiki Kaisha Corporation

Mitsui Toatsu Chemicals, Incorporated

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electronics Corporation

Tower Partners Semiconductor Co., Ltd.

Takayuki Yamada

Masaru Moriwaki

Takashi Nakabayashi

Toshiki Yabu

Masatoshi Arai

Isao Miyanaga

Mizuki Segawa

Takaaki Ukeda

Takashi Uehara

Kyoji Yamashita

Koji Eriguchi

Hideyuki Arai

Takeo Inoue

Michikazu Matsumoto

Masanori Okuyama

Yoshihiro Sato

Takehiro Murao

Hiroaki Nakaoka

Shigeru Kimura

Kazuhiko Yamamoto

Nathan James Smith

Akio Misaka

Satoshi Ishikura

Hiromasa Fujimoto

Tutomu Iwatani

Ryoh Kikuchi

Ryuichi Sugimoto

Kentaro Nakanishi

Akiko Tsunemi

Yukio Ishii

Ryo Nakagawa

Yasuko Tabata

Tomoyo Shiraki

Riichirou Mitsuhashi

Shinsuke Naito

Yoshihiro Mori

Hiroshige Hirano

Tadashi Asanuma

Hisashi Ogawa

Takeshi Yamashita

Tateyo Sasaki

Andrew Acreman

Kenshi Kanegae

Atsuhiro Kajiya

Michinari Yamanaka

Tsutomu Oosuka

Kenji Tateiwa

Hiroaki Kuriyama

Kazuichiro Itonaga

Tomohiro Nishina

Masayuki Kamei

Yasushi Sainoo

Masayuki Nakamura

André Filipe Marques Da Silva

Kohjiroh Morii

Tomoo Imataki

Koji Fukuda

Martin Paul Buckthorpe

Akio Sebe

Hiroji Shimizu

Masatomo Tanahashi

Takashi Kanbayashi

An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

Semiconductor device

Provided is a display device capable of high-quality three-dimensional displaying. During three-dimensional displaying for a viewing position &#x3b2;, in a first term, an entirety of a first predetermined region of a second liquid crystal panel takes on a light-blocking state and a first adjacent region, which is adjacent to the first predetermined region in the first direction, takes on a light-transmitting state. In a second term, at least one of two side regions in the first predetermined region takes on the light-transmitting state, a remaining region of the first predetermined region takes on the light-blocking state, and at least part of the first adjacent region takes on the light-transmitting state.

Display device and liquid crystal panel driving method

The present invention provides a liquid crystal display device capable of performing high-definition and high-luminance dual view display. A liquid crystal display device of the present invention, includes: a first substrate; a second substrate disposed facing the first substrate; a liquid crystal layer disposed between the first substrate and the second substrate; a barrier layer formed on a surface side of the first substrate; a TFT element layer formed on the barrier layer; a pixel electrode laminated on the TFT element layer; a color filter disposed on a liquid crystal layer side of the second substrate; and a counter electrode disposed between the color filter and the liquid crystal layer. The barrier layer includes a barrier pattern formed on the first substrate and an intermediate layer with which the barrier pattern is covered.

Liquid crystal display device

A reconfigurable parallax barrier panel, for use in a display system with a 3D mode, includes a first substrate, a second substrate, and an electro-optic material positioned between the first and second substrates. The first and second substrates each respectively has a plurality of first and second electrodes, the electrodes being independently addressable from one another and comprising a plurality of electrode portions extending along a first direction and laterally spaced from one another along a second direction different from the first direction. The electrode portions of the first electrodes are arranged in a cyclic arrangement having a first pitch, and the electrode portions of the second electrodes are arranged in a cyclic arrangement having a second pitch that is different to the first pitch. The first and second electrodes are driven to generate different reconfigurable parallax barrier arrays corresponding to different viewing distances in a 3D mode of operation.

Dual-pitch parallax barrier

A semiconductor device includes first and second MIS transistors and a dummy element. The first MIS transistor includes a first gate insulating film which includes a first high-k insulating film formed on a first active region and contains an adjusting metal. The second MIS transistor includes a second gate insulating film which includes a second high-k insulating film formed on a second active region and is free of the adjusting metal. The dummy element includes a dummy gate insulating film which includes a dummy high-k insulating film formed on a dummy active region and at least a portion of which is free of the adjusting metal. The first active region is formed in a second conductivity type first well region. The second active region is formed in a first conductivity type second well region. The dummy active region is formed in a second conductivity type third well region.

Provided is a method for manufacturing a solar cell with an interconnection sheet, a method for manufacturing a solar cell module, a solar cell with an interconnection sheet, and a solar cell module. Fixing resin is arranged at least on one side of a location between electrodes of solar cell and a location between interconnections of an interconnection sheet. Thereafter, a first cure state of fixing resin is attained. Thereafter, an adjoining member containing conductive material is provided, and a solar cell and interconnection sheet are stacked to soften the fixing resin exhibiting the first cure state and then re-cure the same to attain a second cure state.

Method for manufacturing solar cell with interconnection sheet, method for manufacturing solar cell module, solar cell with interconnection sheet, and solar cell module

A back electrode type solar cell in which a no-electrode-formed region where no electrode is placed is provided in a part of a peripheral portion of a back surface of the back electrode type solar cell such that a line connecting end portions of a plurality of electrodes to one another includes a partially inwardly recessed region and the no-electrode-formed region is located adjacent to each of an electrode for n-type and an electrode for p-type adjacent to each other, a solar cell module, a method of manufacturing a back electrode type solar cell with interconnection sheet, and a method of manufacturing a solar cell module are provided.

Back electrode type solar cell, back electrode type solar cell with interconnection sheet, solar cell module, method of manufacturing back electrode type solar cell with interconnection sheet, and method of manufacturing solar cell module

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

A first dual-gate electrode includes a gate electrode located on a first active region and having a first silicon film of a first conductivity type and a gate electrode located on a second active region and having a first silicon film of a second conductivity type. A second dual-gate electrode includes a gate electrode located on a third active region and having a second silicon film of the first conductivity type and a gate electrode located on a fourth active region and having a second silicon film of the second conductivity type. At least a portion of the first silicon film of the first conductivity type has a first-conductivity-type impurity concentration higher than that of a portion of the second silicon film of the first conductivity type located on the third active region.

A semiconductor device includes: a plurality of line features including at least one real feature which includes a gate electrode portion, and at least one dummy feature. Two of multiple ones of the dummy feature, and at least one of the line features interposed between the two dummy features and including the at least one real feature form parallel running line features which are evenly spaced. The parallel running line features have an identical width, and line end portions of the parallel running line features are substantially flush. Line end portion uniformization dummy features are formed on extensions of the line end portions of the parallel running line features. The line end portion uniformization dummy features include a plurality of linear features each having a same width as each of the line features and spaced at intervals equal to an interval between each adjacent pair of the line features.

Semiconductor device and layout design method for the same

A semiconductor device includes: a first MIS transistor of a first conductivity type having a first active region as a region of a semiconductor substrate surrounded by an element isolation region formed in an upper portion of the semiconductor substrate, a first gate insulating film having a first high dielectric film formed on the first active region, and a first gate electrode formed on the first gate insulating film; and a resistance element having a second high dielectric film formed on the element isolation region and a resistance layer made of silicon formed on the second high dielectric film. The first high dielectric film and the second high dielectric film include the same high dielectric material, and the first high dielectric film includes a first adjustment metal, but the second high dielectric film does not include the first adjustment metal.

Semiconductor device having gate insulating film including high dielectric material

A semiconductor device includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween; a side wall spacer formed on a side wall of the gate electrode; source/drain regions formed in opposing portions of the semiconductor substrate with the gate electrode and the side wall spacer interposed therebetween; and a stress-applying insulating film covering the gate electrode, the side wall spacer, and an upper surface of the semiconductor substrate. A gate-length-direction thickness of an upper portion of the side wall spacer is at least larger than a gate-length-direction thickness of a middle portion thereof.

Semiconductor device and method for manufacturing the same

The semiconductor device includes a first transistor and a second transistor formed in a semiconductor substrate. The first transistor includes: a first gate insulating film formed on the semiconductor substrate; and a first gate electrode formed on the first gate insulating film. The second transistor includes: a second gate insulating film formed on the semiconductor substrate; and a second gate electrode formed on the second gate insulating film. The first gate insulating film includes a first insulating material with a first element diffused therein, the second gate insulating film includes the first insulating material, and the amount of the first element contained in the first gate insulating film is greater than the amount of the first element contained in the second gate insulating film.

Semiconductor device and fabrication method for the same

A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

Semiconductor device and method for fabricating the same

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Osaka, Japan

Takayuki Yamada