Asahi Kasei Kogyo Kabushiki Kaisha

Asahi Kasei Kabushiki Kaisha

Asahi Kasei Electronics Co., Ltd.

Takayuki Watanabe

Tetsuya Yamamoto

Hiroshi Yoshida

Yoshihiko Shibata

Takashi Yoshida

Akihiko Oyama

Tsuyoshi Ujihara

Hidenobu Nakazawa

Hall device is provided by enabling stable provision of a quantum well compound semiconductor stacked structure. It has first and second compound semiconductor layers composed of Sb and at least two of five elements of Al, Ga, In, As and P, and an active layer composed of InGaAsSb(0.8&#x2266;x&#x2266;1.0, 0.8&#x2266;y&#x2266;1.0), which are stacked. Compared with the active layer, the first and second compound semiconductor layers each have a wider band gap, and a resistance value five times or more greater. The lattice constant differences between the active layer and the first and second compound semiconductor layers are each designed in a range of 0.0-1.2%, and the thickness of the active layer is designed in a range of 30-100 nm.

Compound semiconductor multilayer structure, hall device, and hall device manufacturing method

A solar cell having a semiconductor layer of a chalcopyrite structure as a light absorption layer and using a flexible film as a substrate, breakdown and peeling caused to the semiconductor layer of the chalcopyrite structure due to warp of the flexible film upon heat treatment is prevented. To realize this, a poly(phenylene terephthalmide) film having a coefficient of heat expansion of 5.0&times;10,/&deg; C. is used as a substrate (,). After a Ti reinforcing layer (,) is disposed on the entire back surface of this substrate (,), a first electrode layer (,) is disposed on the front surface of this substrate (,), and a p-type semiconductor layer (,) of a chalcopyrite structure is formed as a light absorption layer on the surface of the first electrode layer (,).

Solar cell and manufacturing method thereof

p-type semiconductor, method for manufacturing the p-type semiconductor,

Growing community of inventors

Fuji, Japan

Takayuki Watanabe