Fujitsu Corporation

Takayuki Tsuru

Hideki Harada

Takushi Motoyama

Kazumasa Nawata

Toshiaki Sakai

Taichi Saitoh

Hiroyuki Tsunoi

Hiroki Yada

Hisayosi Ooba

Satoru Sudo

A reticle is designed with a method including generating first dummy patterns with intervals from main patterns. Each of the first dummy patterns are divided into a plurality of spaced apart second dummy patterns and then each of the second dummy patterns are measured to find third dummy patterns having widths and areas below smallest allowable values. The third dummy patterns are then respectively connected to second dummy patterns which are adjacent to the third dummy patterns by generating a connecting dummy pattern. Selective non-connected third dummy patterns are removed. The first dummy patterns are divided into a plurality of second dummy patterns by vertical and horizontal strip lines crossing the first dummy patterns.

Method for designing reticle, reticle, and method for manufacturing semiconductor device

A reticle is designed with a method including a step of generating first dummy patterns with intervals from main patterns. Each of the first dummy patterns are divided into a plurality of spaced apart second dummy patterns and then each of the second dummy patterns are measured to find third dummy patterns having widths and areas below smallest allowable values. The third dummy patterns are then respectively connected to second dummy patterns which are adjacent to the third dummy patters by generating a connecting dummy pattern. Selective non-connected third dummy patterns are removed. The first dummy patterns are divided into a plurality of second dummy patterns by vertical and horizontal strip lines crossing the first dummy patterns.

Method for designing reticle, reticle, and method for manufacturing

A logic circuit in which first and second transistors are connected in series between high and low potential power sources with the middle point of the series connection used as the output terminal; A same- and inverse-phase signal generating unit is provided connected between the high and low potential power sources in parallel with the first and second transistors for generating same- and inverse-phase signals based on the single input signal output from the logic circuit. A transient signal generating unit is provided for generating transient large current signals at the rise time of the inverse-phase signals and generating transient cut-off signals at the fall time of the inverse-phase signals. The series connected first transistor is driven and controlled based on the regular-phase signals, while the second transistor is driven and controlled based on the transient large current signal and transient cut-off signal, thus producing an inverse-phase output by a simple circuit construction.

Logic circuit having sharper falling edge transition

Growing community of inventors

Kawasaki, Japan

Takayuki Tsuru