Kabushiki Kaisha Toshiba

Kioxia Corporation

Renesas Electronics Corporation

Toshiba Memory Corporation

Taiyo Yuden Co., Ltd.

Sandisk Corporation

Mizuho Research & Technologies, Ltd.

Rikkyo Educational Corporation

Takayuki Tsukamoto

Hiroshi Kanno

Yoichi Minemura

Takamasa Okawa

Kohichi Kubo

Tsukasa Nakai

Chikayoshi Kamata

Shinya Aoki

Takahiro Hirai

Atsushi Yoshida

Akiko Hirao

Sumio Ashida

Takafumi Shimotori

Reika Ichihara

Kazuki Matsumoto

Takeshi Yamaguchi

Toshiro Hiraoka

Keiichiro Yusu

Naomasa Nakamura

Hideyuki Nishizawa

Noritake Oomachi

Hideyuki Tabata

Urara Ichihara, Legal Representative

Kenichi Murooka

Katsutaro Ichihara

Tomonori Kurosawa

Mizuki Kaneko

Hirofumi Inoue

Rumiko Hayase

Mariko Hayashi

Mitsuru Sato

Takeshi Araki

Takahiko Sasaki

Jun Nishimura

Takashi Shigeoka

Natsuki Kikuchi

Masahiro Une

Masanori Komura

Takeshi Nakayama

Akira Kikitsu

Katsuyuki Naito

Katsuyuki Sekine

Takayuki Ishikawa

Yuichi Okuda

Fumihiko Aiga

Yoshinori Honguh

Kenji Todori

Tatsuji Matsuura

Mutsumi Okajima

Nobuaki Yasutake

Hiroyuki Fukumizu

Hisashi Kato

Takeshi Sugimoto

Fumitoshi Ito

Nobuyuki Yamazaki

Nobuhisa Yoshida

Yoshiyuki Wasada

Hironobu Furuhashi

Yasushi Inoue

Satoshi Konagai

Atsushi Motozawa

Takefumi Endo

Junichi Shimamura

Yuji Mochizuki

Mitsuaki Ootani

Tetsuji Kunitake

Noritake Ohmachi

Kaori Fukuzawa

Yuji Ebinuma

Katsutaro Ichihara, Deceased

Koichiro Zaitsu

Youichi Minemura

Hironori Wakai

Mutsuya Motojima

A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.

Semiconductor device and memory system

A semiconductor integrated circuit includes a bandgap reference circuit that includes a first bandgap element, a second bandgap element, and a current mirror circuit. The bandgap reference circuit is configured to generate a temperature-dependent first voltage and a temperature-independent reference voltage. The semiconductor integrated circuit includes an analog-to-digital converter configured to convert the first voltage into an output code based on the reference voltage and output the first voltage as temperature information, and a setting control circuit configured to change at least one setting of the bandgap reference circuit based on the temperature information.

Semiconductor integrated circuit with configurable setting based on temperature information

A semiconductor integrated circuit includes a first oscillator configured to generate a first signal with a first frequency based on a control signal and output the first signal to a path. The semiconductor integrated circuit includes a control signal generation circuit operatively coupled to the first oscillator via the path, and configured to receive the first signal from the first oscillator via the path and generate the control signal. The semiconductor integrated circuit includes a second oscillator configured to generate a second signal with a second frequency based on the control signal and output the second signal to an output terminal outside the path.

Semiconductor integrated circuit, semiconductor storage device, memory system, and frequency generation method

A device for creating a fragment model from a crystal model is equipped with a division position identifying section adapted for identifying multiple division atom pairs for multiple atoms contained in the crystal model. The atoms in the division atom pairs are contained in different fragment models. The device is additionally equipped with a model creating section adapted for identifying each of multiple atom groups each composed of atoms bonded to each other in the crystal model and for creating fragment models respectively corresponding to the identified atom groups.

Device, system, method and program for producing fragment model

A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.

Semiconductor memory device

A semiconductor storage device includes first to third wirings extending in a first direction and adjacent in a second direction intersecting the first direction, fourth to sixth wirings extending in the second direction and adjacent in the first direction, memory cells each having one end connected to one of the first to third wirings and the other end connected to one of the fourth to sixth wirings, a circuit configured to output a first voltage, second and third voltages higher than the first voltage, a fourth voltage higher than the second voltage and the third voltage, and a fifth voltage higher than the fourth voltage. In a write operation for memory cells connected to the first and fourth wirings, the first, fourth, second, fifth and third voltages are transferred to the first, second, third, fourth, and fifth wirings, respectively, and the third voltage is transferred to the sixth wiring.

Semiconductor storage device

A semiconductor memory device includes a control circuit, first wirings, second wirings intersecting the first wirings, and memory cells formed between the first wirings and the second wirings. The control circuit is configured to supply, in a set operation, a set pulse between one of the first wirings and one of the second wirings, supply, in a reset operation, a reset pulse between one of the first wirings and one of the second wirings, and supply, in a first operation, a first pulse between one of the first wirings and one of the second wirings. The first pulse has an amplitude larger than a larger one of an amplitude of the set pulse or an amplitude of the reset pulse, or the same amplitude as the larger amplitude. The first pulse has a pulse width larger than a pulse width of the reset pulse.

A storage apparatus according to embodiments includes: a first interlayer insulating film extending in a first direction; a second interlayer insulating film extending in the first direction; a first conductive layer extending in the first direction and provided between the first interlayer insulating film and the second interlayer insulating film; a second conductive layer extending in a second direction intersecting the first direction; a resistance change layer including a first portion provided between the first interlayer insulating film and the second interlayer insulating film and including a second portion provided between the second conductive layer and the first interlayer insulating film, between the second conductive layer and the first conductive layer, and between the second conductive layer and the second interlayer insulating film; and a sidewall insulating film provided between the first portion and the first interlayer insulating film and between the first portion and the second interlayer insulating film.

Storage apparatus

A method for controlling a resistive memory device is described. The resistive memory device including a memory cell provided between a first interconnection and a second interconnection crossing the first interconnection, and the memory cell transitions reversibly between a first resistance state and a second resistance state. The method includes detecting a first current flowing through a memory cell by applying a first voltage between the first interconnection and the second interconnection; comparing a value of the first current with a first criteria value; and determining whether the memory cell is in the first resistance state or the second resistance state. The method further includes comparing the value of the first current with a second criteria value greater than the first criteria value; and setting a first flag for the memory cell when the value of the first current is greater than the second criteria value.

Method for controlling resistive memory device

A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes: a plurality of first conductive layers that are stacked; a memory layer provided on a side surface of the plurality of the first conductive layers; and a second conductive layer that contacts the side surface of the plurality of the first conductive layers via the memory layer. A thickness of the first conductive layer disposed at the first position is larger than a thickness of the first conductive layer disposed at the second position. The control circuit is configured to apply a first voltage to a selected first conductive layer. The control circuit changes a value of the first voltage based on a position of the selected first conductive layer.

Three-dimensional resistive memory device with adjustable voltage biasing

A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction. The interlayer insulating film also includes an insulating film positioned above the air gap and having a curved surface that protrudes toward a direction of the substrate.

This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.

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Yokkaichi, Japan

Takayuki Tsukamoto