Sharp Kabushiki Kaisha Corporation

Takayuki Taniguchi

Hiroki Tabuchi

Makoto Tanigawa

Hiroyuki Moriwaki

Katsuji Iguchi

Takuji Tanigami

Shinichi Sato

Naoyuki Shinmura

Keiichi Sawai

Kenji Hakozaki

Masanori Yoshimi

Akio Shimoyama

Hajime Oda

Masahiro Saitoh

Hiroki Tanigami

A semiconductor memory device comprises a memory cell array including memory cells arranged in matrix each having a selective transistor and a variable resistance element having an electric resistance changed from a first state to a second state by applying a first write voltage and from the second state to the first state by applying a second write voltage. A first write current for a first writing operation to change the electric resistance from the first state to the second state is larger than a second write current for a second writing operation to change it from the second state to the first state. A second memory cell number of memory cells subjected to the second writing operation at a time is greater than a first memory cell number of memory cells subjected to the first writing operation at a time. At least the second memory cell number is plural.

Semiconductor memory device with variable resistance elements

A method of manufacturing a semiconductor device can suppress the generation of burrs when an array of integrated circuits to which a supporting member is bonded for assistance is separated into chips. The supporting member having thinned regions (or void regions which are openings in the supporting member) located correspondingly beneath the scribing lines extending between the integrated circuits is bonded by an adhesive to the back side of a semiconductor substrate on which integrated circuits are arrayed at the primary side. Then, a dicing tape is attached to the support member to secure the entire assembly, and the assembly of the integrated circuits, the semiconductor substrate, the adhesive, and the supporting member are cut along the scribing lines, and then the dicing tape is removed.

Semiconductor device and manufacturing method thereof

The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.

Process for fabricating a semiconductor device

A method for forming a fine resist pattern by exposing comprising the steps of: (i) forming a resist layer on a semiconductor substrate; (ii) forming a phase shifting pattern in an upper portion of the resist layer, the phase-sifting pattern having a tapered edge corresponding to a portion to which formation of an objective fine resist pattern is not desired; (iii) exposing the entire surface of the semiconductor substrate including the phase-shifting pattern; and (iv) forming a fine resist pattern below an outline except for the tapered edge of the phase-shifting pattern.

Method for forming a fine resist pattern

In the system according to the present invention detects defects by projecting illumination light for exposure having a certain wavelength perpendicularly onto a phase shift mask to be examined; picking up, by means of an image acquisition section, two pattern images which are formed from the irradiated light having passed through two neighboring dies on the phase shift mask and image-formed individually through respective magnifying projection optical systems, and superposing the image patterns of two dies through an alignment to compare therebetween.

Defect inspection system for phase shift masks

A method for forming a resist mask pattern by light exposure providing the steps of forming a resist layer on a semiconductor substrate, forming a phase shifter pattern for inverting a phase of exposed light in an upper portion of the resist layer itself or over the surface of the resist layer, exposing the surface of the semiconductor substrate including the phase shifter pattern, and forming a fine mask pattern below the edge of the phase shifter pattern.

Growing community of inventors

Kitakatsuragi-gun, Japan

Takayuki Taniguchi