Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Solid State Storage Solutions LLC

Renesas Electronics Corporation

Other

Toshiba Memory Corporation

Takayuki Tamura

Kunihiro Katayama

Shigemasa Shiota

Kiyoshi Inoue

Masashi Naito

Satoshi Watatani

Hiroyuki Goto

Hirofumi Shibuya

Motoki Kanamori

Atsushi Shikata

Koichi Kimura

Hideki Kamimaki

Yasuhiro Nakamura

Hitoshi Kawaguchi

Kazushi Kobayashi

Yusuke Jono

Shinsuke Asari

Nagamasa Mizushima

Ken Matsubara

Tomoyuki Fujisawa

Takashi Totsuka

Keiichi Yoshida

Jun Kitahara

Atsushi Nozoe

Atsushi Shiraishi

Toru Owada

Kenji Kozakai

Yoshinori Takase

Chiaki Kumahara

Takeshi Asahi

Takashi Horii

Kazuo Nakamura

Yasushi Akao

Ikuya Kawasaki

Kazunori Furusawa

Tsuguji Tachiuchi

Tomihisa Hatano

Koichi Isaji

Akira Hikimura

Tetsuya Iida

Shinichi Sawamura

Shinichi Shuto

Masatomi Sasaki

According to one embodiment, a memory system includes, as an example, a temperature information receiver that receives temperature information; and a gradient determining unit that determines a gradient related to a temperature increase, based on the temperature information about a plurality of temperatures received by the temperature information receiver.

Memory system, memory controller and control device

A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.

External storage device and memory access control method thereof

A nonvolatile memory apparatus includes a control unit, a main storage medium with an electrically reloadable nonvolatile memory adapted to be operable even when faulty memory cells exist therein, and a storage region storing registered address values of faulty regions of the main storage medium containing the faulty memory cells. Data which is stored in the electrically reloadable nonvolatile memory is divided into blocks, each block having a plurality of data to be administrated and which is assigned an access address by the control unit. An administrative information region is provided in each block. The control unit carries out access requests of the main storage medium and the administration of faulty regions and the number of occurrences of reloading of respective memory cells of the main storage medium.

Semiconductor memory device having faulty cells

In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Nonvolatile memory with faulty cell registration

In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.

Semiconductor memory having electrically erasable and programmable semiconductor memory cells

A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Memory card and memory controller

An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.

A non-volatile storage device () has non-volatile memory units (FARYto FARY), buffer units (BMRYto BMRY) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

Non-volatile memory having multiple erase operations

Growing community of inventors

Yokohama, Japan

Takayuki Tamura