Fujitsu Corporation

Pfu Limited

Takayuki Shimamura

Hirohide Sugahara

Akira Kabemoto

Toshiyuki Muta

Takatsugu Sasaki

Yozo Nakayama

Jun Sakurai

Junji Nishioka

Naohiro Shibata

Satoshi Shinohara

Takeshi Horie

Toshiyuki Shimizu

Hiroaki Ishihata

Yasuyuki Umezaki

Shinya Kato

Takato Noda

Minoru Kawarabayashi

Takumi Nonaka

Tatekuni Onoue

A speed converting apparatus with a load controlling function comprises a first interface unit operating for an emulation device according to a system clock of the emulation device, a second interface unit operating for an arithmetic unit according to a system clock of the arithmetic unit, and a load controlling unit controlling at least either a load of a request outputted to the emulation device on the emulation device or a load of a request outputted to the arithmetic unit on the arithmetic unit. In performance verification or connection verification of a target to be verified, the speed converting apparatus can vary a load of a request issued to the target to be verified on the target or a load issued to a verification device on the verification device, while absorbing a difference in operation speed between the target to be verified and the verification device.

Speed converting apparatus with load controlling function and information processing system

To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.

Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

Multiprocessor, memory accessing method for multiprocessor, transmitter

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.

Coherence apparatus for cache of multiprocessor

Growing community of inventors

Kawasaki, Japan

Takayuki Shimamura