Nec Corporation

Nippon Steel Corporation

Ngk Insulators, Inc.

Dai Nippon Printing Co., Ltd.

Tokyo Electric Power Company Holdings, Inc.

Takayuki Shibata

Kazuhiro Abe

Yoshinori Narita

Toshifumi Sato

Hideo Ohmura

Yoichiro Tashiro

Yuzuru Sasaki

Masataka Kurokawa

Youko Kimura

A storage battery system control method includes at least the following steps. Respective current SOC (state of charge) values of the large capacity storage battery system and the high power storage battery system are acquired. Electrical power, which is required to operate the frequency control service for the purpose of suppressing frequency fluctuations, to the large capacity storage battery system and the high power storage battery system, in accordance with the respective SOC values. The respectively allocated electrical power is charged or discharged by driving the large capacity storage battery system, or alternatively, the high power storage battery system, or alternatively, the large capacity storage battery system and the high power storage battery system.

Method for controlling storage battery system

Realization of a configuration of decorative sheet, particularly a decorative paper, or a decorative material in which it is adhered, meaning: a grain depression is not visible; excellent in scratch resistance, also in contamination resistance; and three-dimensional design can be expressed. The configuration is realized by using delustering silica, whose surface is treated with a fatty acid based wax such as stearic acid, in a decorative materialin which a luster adjusting resin layer, formed of a cross-linked cured material of an ionizing radiation curing resin composition containing a delustering silica, is on base material

Decorative material and decorative sheet

A CDMA adaptive antenna reception apparatus is provided. The apparatus includes N adaptive antenna reception sections and an initial antenna weight production section. Each of the reception sections includes an initial antenna weight selection section, which selects initial values from initial antenna weight candidates, an antenna weight control section, which adaptively controls antenna weights, and antenna weighting synthesis sections, each of which multiplies signals received by K antennae by the antenna weights and synthesizes the results of the multiplication to detect a desired signal. The initial antenna weight production section detects beam directions and null directions from antenna weights of desired signals. A null formation direction discrimination section estimates a null direction of a new desired signal, and an initial antenna weight candidate production section produces initial antenna weight candidates with which the null is formed in the estimated null direction in order to detect the new desired signal.

Adaptive antenna reception apparatus

A maximum likelihood sequence estimation (MLSE) apparatus which can estimate a maximum likelihood sequence (MLS) correctly, even when an optimum range of an impulse response is changed, includes a range setting device for selecting an optimum range in the impulses detected by an impulse response detector. The MLSE apparatus estimates the MLS by using the impulses in the optimum range as the tap coefficients which are renewed by adaptive estimation in an adaptive control device. The range setting device renews the optimum range, every time the tap coefficients are renewed. The adaptive control device sets up the impulses in the optimum range as the tap coefficients in MLSE means. The MLSE apparatus estimates MLS on the basis of the impulses in the optimum range.

Maximum likelihood sequence estimation apparatus

In a receiving device, a mixer combines a frequency which is different from a carrier frequency by (2n&plus;&frac12;)&ohgr; and a reception signal, provided that n is an integer, &ohgr; &equals;2&Pi;/T, and T is a transmission rate of a base band signal, a filter takes out a base band signal of a center frequency of (2n&plus;&frac12;)&ohgr; and removes a DC component, so as to sample the signal and put it through A/D conversion, a multiplier combines the signal and a polarity signal, so as to obtain an in-phase component p(nT) of the reception signal at time nT and an orthogonal component q&lsqb;(n&plus;&frac12;)T&rsqb; of the reception signal at time (n&plus;&frac12;)T. A branch metric is calculated and maximum likelihood sequence estimation is executed on the basis of those components and a replica signals pR(nT) and qR&lsqb;(n&plus;&frac12;)T&rsqb;, so as to estimate a signal sequence. Thus the receiving device exhibits improved performance as it is capable of eliminating any phase difference and amplitude difference between Ich and Qch and any DC offset, without requiring any large-scale additional circuit.

Receiving device with demodulating function based on orthogonal detection and equalizing function based on maximum likelihood sequence estimation

An adaptive equalizer includes an impulse response detecting section, a region specifying section, an adaptive control section and a delayed decision feedback sequence estimating section. The impulse response detecting section detects an impulse response of a transmission path from a training signal. A reception signal includes the training signal and a data signal following the training signal. The region specifying section outputs a region specifying signal used to specify a sequence estimation region and an adaptive control region of the detected impulse response. The adaptive control section updates the detected impulse response using an adaptive algorithm based on the data signal and an estimation result, and outputs the updated impulse response for the determined sequence estimation region. The delayed decision feedback sequence estimating section performs a sequence estimation based on the updated impulse response for the determined sequence estimation region and the data signal to produce the estimation result, and outputs the estimation result to the adaptive control section.

Adaptive equalizer compensating signal distortion on transmission path

A sorting apparatus in which, while its scale is limited so as not to become large, all of base axis data supplied as its input are sorted in order, and, at the same time, the sorted base axis data are outputted in the sorted order. The sorting apparatus includes a plurality of sorter sections, a base axis data train divider section for supplying partial base axis data trains to these sorter sections, and a comparative result output section for merge/sorting (comparatively selecting) the results of sorting of the individual partial base axis data trains in the plural sorter sections and sequentially outputting the sorted ones of the base axis data in the sorted order. Thus, in the sorting apparatus, base axis data are divided into a plurality of partial base axis data trains, and, after the partial base axis data trains are partially concurrently sorted in the plural sorter sections, the base axis data are sequentially outputted from the comparative result output section in the sorted order.

Parallel merge sorting apparatus with an accelerated section

In order to realize control of a transmission signal level from a radio transmitter of TDMA (Time Division Multiplex System) with a simplified arrangement and with a high precision, a control circuit 9 outputs a transmission signal for each time slot and a level designation signal. A level control signal generator circuit 4 generates a level control signal in response to the level designation signal and outputs the level control signal through D/A converter 5 to a level control circuit 2. The level of the modulated transmission signal is controlled by the level control circuit 2 and is amplified by a RF amplifier circuit 3 thereby being output outside. The output level is detected by a detector circuit 8 and fedback through A/D converter 7 and a detection characteristic storage circuit 8 to level control signal generator circuit 4 so that the value of the level control signal is corrected.

Transmission signal level control device for radio transmitter

A data demodulator wholly consisting of digital circuits for time division multi-access (TDMA) signals subjected to differential phase-shift-keying (DPSK) is provided. The data demodulator generates a phase difference signal by subjecting .pi./4-shift quadrature phase-shift-keying (.pi./4 QPSK) signals to delayed detection of phase in synchronism with N-phase clock signals (where N is a positive integer), and reproduces a resulting phase difference signal into decision data. A first such data demodulator detects decision errors from the phase difference signal and decision data, and achieves symbol synchronism by sampling the decision data in a clock signal phase involving little decision error. A second such data demodulator supplies the phase difference signal after correcting its D.C. offset due to a frequency drift. In these two data demodulators, the formulas for computing said decision errors and correction values are flexibly varied according to preceding burst information.

Data demodulator

A digital modulator comprises a power control circuit for producing a digital power control signal, first and second digital multipliers for multiplying digital signals having orthogonal phase relationships with the digital power control signal, and first and second digital-to-analog (D/A) converters for converting digital output signals from the first and second multipliers into analog signals. First and second low-pass filters are connected to outputs of the D/A converters, respectively, to filter out high frequency components. An orthogonal modulator is provided for mixing orthogonal phase carriers with the outputs of the first and second low-pass filters to produce first and second orthogonally modulated signals and combining the modulated signals to produce a transmit signal, which is amplified for transmission.

Digital modulator with digital power control circuit

A versatile detection apparatus for acquisition of various data from objects using a plurality of different detection sensors acquiring information from the object and a preselected first memory storing computation procedures for adapting apparatus to the selected detection sensors comprises first connection members for detachably connecting the selected detection sensors to the detection apparatus, second connection members for detachably connecting the first memory to the detection apparatus, and an inspection device for inspecting coincidence between the selected detection sensors connected to the first connection members and the preselected memory connected to the second connection members.

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Tokyo, Japan

Takayuki Shibata