Fujitsu Corporation

Fijitsu Limited

Takayuki Shibasaki

Hirotaka Tamura

Yukito Tsunoda

Taiki Uemura

Toshiyuki Miyazawa

Satoshi Matsubara

Motomu Takatsu

Sanroku Tsukamoto

Takuji Yamamoto

Masaya Kibune

Yasufumi Sakai

Ali Sheikholeslami

Noboru Yoneoka

Jumpei Koyama

Akihiko Ohwada

Kazuya Takemoto

Wahid Rahman

A device including: defining unit to define lattice space that is collection of lattices compound groups are sequentially arranged; limiting unit to, in the case where any of the compound groups is arranged in any of the lattices of lattice space followed by arranging next compound group in the lattice space, generate limited lattice space created by eliminating, from the lattice space, undesirable regions for the next compound group to be arranged; and assigning unit to assign bit to each of lattice points, to which the compound groups can be arranged, in the limited lattice space; and an arithmetic unit configured to perform ground state search on Ising model obtained through conversion based on restriction conditions related to each lattice point according to simulated annealing, to calculate minimum energy of the Ising model, wherein the device is for searching compound in which the compound groups are linked with one another.

Device and method for searching compound

A problem is inputted into an operation unit. A computation unit searches for a ground state of an Ising model. A management unit converts the problem inputted from the operation unit to the Ising model, inputs the Ising model produced by conversion and initial operating conditions into the computation unit, and has the computation unit search for the ground state using overall operating conditions produced by changing the initial operating conditions based on a result of the computation unit searching for the ground state using the initial operating conditions.

Optimization apparatus and control method for optimization apparatus using ising models

In an optimization apparatus, a computing unit searches for the ground state of an Ising model generated by converting an optimization problem to be solved, based on Ising model information representing the Ising model and a temperature parameter. A control unit determines the minimum value of the temperature parameter, based on a resolution in energy of the computing unit for the Ising model and a first reference value indicating an acceptance probability of state transition in the Ising model at the minimum value, determines a maximum amount of change in energy, based on the Ising model information, determines the maximum value of the temperature parameter, based on the determined maximum amount of change in energy and a second reference value that is greater than the first reference value and indicates the acceptance probability at the maximum value, and sends the minimum and maximum values to the computing unit.

Optimization apparatus and control method thereof

A transition control unit detects, when stochastically determining based on a temperature, energy changes, and a random number whether to accept any of a plurality of state transitions according to a relative relationship between the energy changes and thermal excitation energy, a minimum value among the energy changes. The transition control unit then subtracts, when the minimum value is positive, an offset obtained by multiplying the minimum value by a value M that is greater than 0 and less than or equal to 1 from each of the energy changes corresponding to the plurality of state transitions.

An optimization apparatus includes a memory; and a processor coupled to the memory and the processor configured to: compute a local solution for a combinatorial optimization problem based on a first evaluation function representing the combinatorial optimization problem, select a state variable group targeted by partial problems from the plurality of state variables based on a first state variable whose value at the local solution is a predetermined value among the plurality of state variables included in the first evaluation function, a weight coefficient representing a magnitude of an interaction between the plurality of state variables held in a storage unit, and input selection region information, search a ground state for a second evaluation function representing the partial problems for the selected state variable group, and generate a whole solution by updating the local solution based on the partial solutions acquired by the ground state search.

Optimization apparatus, control method for optimization apparatus, and recording medium

An optical transmitter includes: an optical modulator, a phase adjustment circuit, first and second synchronization circuits, and first and second drive circuits. The optical modulator includes a first modulation area and a second modulation area that is provided at output side of the first modulation area. The phase adjustment circuit adjusts a phase of a first clock signal so as to generate a second clock signal. The first and second synchronization circuits respectively output first and second electric signals in synchronization with the first and second clock signals. The first and second drive circuits respectively drive the first and second modulation areas with the first and second electric signals.

Optical transmitter that includes optical modulator

A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.

CDR circuit and receiving circuit

A CDR circuit includes a data-determination-circuit to determine a value of a data-signal, based on a first comparison-result of comparing the data-signal with first threshold-values at a timing of a clock-signal, a comparison-circuit to compare the data-signal with a second threshold-value at the timing to generate a second comparison-result, a phase-detection-circuit to detect data-patterns in which first to third symbols are temporally consecutive, based on a determination-result, the data-patterns forming that a value of the second symbol is larger than the first symbol and smaller than the third symbol, or the in value of the second symbol is smaller than the first symbol and larger than the third symbol, wherein the phase-detection-circuit generates a phase-difference-signal for controlling a phase of the clock-signal to advance or delay, based on the second comparison-result at the second symbol, and a phase-adjustment-circuit to adjust the phase of the clock-signal based on the phase-difference-signal.

CDR circuit and reception circuit

A comparator circuit outputs a comparison result obtained by comparing a data signal with a threshold whose magnitude is adjusted based on a first offset value at a timing synchronized with a second clock signal whose phase is adjusted based on a difference in phase between the data signal and a first clock signal and a second offset value. An eye monitor circuit thins comparison results obtained in a clock data recovery (CDR) circuit for individual symbols of the data signal by comparing the data signal with a threshold, selects a comparison result corresponding to a symbol for which the comparison result is obtained by the comparator circuit, determines, by comparing the selected comparison result with the comparison result obtained by the comparator circuit, whether or not an error has occurred due to the first or second offset value, and outputs the number of times the error has occurred.

Receiver circuit and eye monitor system

A clock data recovery circuit includes an oscillator that outputs a first clock and a second clock having the same frequency and a different phase, and a feedback circuit that controls the oscillator so as to synchronize input data and the first clock, the feedback circuit including a controller that controls the oscillator in response to a frequency difference signal and a phase difference signal, a first difference detector that generates a first difference signal, a second difference detector that generates a second difference signal, and a frequency detector that outputs the frequency difference signal based on the first difference signal and the second difference signal, the frequency detector including a state detector that detects one of the rising state or the falling state, and a state holder that holds a state detected in the first phase and outputs the frequency difference signal.

Clock data recovery circuit, electronic device, and clock data recovery method

A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses.

Reception circuit

A termination resistance adjustment circuit includes a replica circuit having the same characteristics as drive circuits; a current source being able to adjust the amount of a load current of the replica circuit; a voltage generation circuit to generate a plurality of reference voltages respectively corresponding to a plurality of values of the input data with the plurality of bits; a comparison circuit to compare an output voltage of the replica circuit with the reference voltages; and a control circuit to change the amount of the load current by controlling the current source, to calculate values of the output resistances of the replica circuit for each of the plurality of levels, and to adjust the number of use of the drive circuits for each bit of the input data, based on the calculated values of the output resistances for each of the plurality of levels.

Termination resistance adjustment circuit and device including termination resistance adjustment circuit

A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.

Frequency detection circuit and reception circuit

A receiving circuit includes circuits arranged in parallel, each circuits including a voltage-controlled-oscillator (VCO) configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and a gain circuit. Each circuit is configured to sample a piece of input data with an output clock of the VCO and adjust the oscillation frequency of the VCO based on a phase difference and a frequency difference between the piece of input data and the output clock, thereby recovering data and a clock based on the piece of input data. The gain circuit is configured to adjust ratios of gains of up and down of the oscillation frequency of the VCO in a loop in each circuit arranged adjacent to each other, based on a phase difference between the pieces of input data and a phase difference between the output clocks of the respective circuits.

Receiving circuit

A multi-lane re-timer circuit includes: a clock generation circuit to generate a base clock; and reception circuits to generate a reception clock and receive input data signals from lanes, wherein each of the reception circuits includes: a phase frequency detector to generate phase difference signal and frequency difference signal between the input data signal and the reception clock; a clock data regeneration controller to generate a control signal based on the phase difference signal; a phase rotator to generate the reception clock from the base clock; and a decision circuit to receive the input data signal, and wherein the clock generation circuit includes: an input selector to select a signal; a charge pump to generate a charge signal; a loop filter to remove a high frequency component from the charge signal to output a voltage control signal; and a voltage controlled oscillator to generate the reception clock.

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Kawasaki, Japan

Takayuki Shibasaki