Fujitsu Corporation

Fujitsu Semiconductor Limited

Takayuki Sasaki

Ryuichi Takechi

Hideaki Ono

Hiroshi Sasaki

Ryuji Fujita

Junichi Niitsuma

Tsuguo Kato

Kazuhide Tamaki

Kenji Abe

Kaoru Yokoo

Takahiro Suzuki

Satoshi Mikami

Shigeru Satoh

Takashi Tokue

Hirohisa Kotegawa

Tatsuro Miyakawa

There is provided an information processing apparatus among a plurality of information processing apparatuses included within an information processing system, the information processing apparatus including a memory, a processor coupled to the memory and configured to perform information processing, and a controller configured to acquire a plurality of sensor data items output from each a plurality of sensors arranged in a liquid cooling system cooling the plurality of information processing apparatuses and abnormality information relating to the liquid cooling system stored by another information processing apparatus among the plurality of information processing apparatuses, detect an abnormality of the liquid cooling system based on the acquired sensor data items and the abnormality information, obtain a range of influence of the detected abnormality of the liquid cooling system based on the detected abnormality, and control the information processing apparatus based on the range of influence.

Information processing apparatus and information processing system

In a power estimator, a power coefficient-calculating section acquires an average value of the number of signal changes per unit time in each circuit range to thereby calculate a power coefficient for each circuit range or calculate a power coefficient for each circuit range when the average value of the number of signal changes per unit time is equal to 1, a correction coefficient-calculating section calculates a ratio of an average value of the number of signal changes per unit time at signal lines included in the circuit range to an average value of the number of signal changes per unit time at observing points designated in the circuit range, as a correction coefficient, and a power value-calculating section calculates a power value for each circuit range based on the correction coefficient and the power coefficient calculated for each circuit range.

Method and system for power estimation based on a number of signal changes

As a program tool of the embodiment estimating the peak of power consumption, primary processing is performed in which logic simulation is executed in a first time period to extract operation data of a gated clock for every predetermined section within the first time period, e.g. operation waveform data or data on the number of operations. Then, a narrowed section, which is composed of one or more sections and in which the switching activity per unit time is higher compared to other sections, is discovered, the switching activity being obtained from the operation data, and this narrowed section is taken as a second time period. Then, secondary processing is performed in which logic simulation is executed in the second time period to extract signal waveform data for every clock cycle and obtain power consumption data corresponding to the clock cycles from the extracted signal waveform data.

Power consumption peak estimation program for LSI and device therefor

Disclosed is a power consumption analysis method capable of reducing an analysis time of power consumption. The method is performed on a design circuit having a characteristic signal for specifying an operating mode of a circuit block and the method comprises the steps of: measuring an operating rate of the characteristic signal in each unit analysis interval for analyzing the power consumption; determining, based on measurement results of the operating rate of the characteristic signal, whether to measure the operating rate of the circuit block whose operating mode is specified by the characteristic signal; and measuring the operating rate of the circuit block only when determined to measure the operating rate of the circuit block.

Method and apparatus for analyzing power consumption

A power consumption analyzing method, to be implemented by a computer, is for a circuit developing procedure that makes a logic design of the circuit in an RTL design stage and inserts a gated clock with respect to the circuit in a subsequent logic synthesis stage. The method comprises an extraction step, implemented by the computer, extracting a signal which is judged that it will be transformed into a gated clock in the logic synthesis stage, and storing the signal in a memory part, a measuring step, implemented by the computer, measuring an valid time of the signal stored in the memory part by a logic simulation, and storing the valid time in the memory part, and a post-simulation step, implemented by the computer, computing a power consumption analysis result of the circuit from the valid time stored in the memory part, a number of registers for each of modules that are function units forming the circuit, and a memory capacity coefficient indicating an extent to which a memory capacity within the circuit affects the power consumption of the circuit, and outputting the power consumption analysis result.

Power consumption analyzing method and computer-readable storage medium

A verification support device supports logic verification of a design object corresponding to modified sequence diagrams obtained by modifying sequence diagrams expressing processes of a design object in a chronological order. A diagram extracting unit extracts the modified sequence diagrams. A modified process detecting unit detects modified processes by comparing the sequence diagrams before modification and the sequence diagrams after modification. Based on the modified processes, an applicability determining unit determines whether test benches used for a regression test of the design object of the sequence diagrams before modification is applicable to a regression test of the design object of the sequence diagrams after modification. A test bench output unit outputs test benches based on a result of determination by the applicability determining unit.

Verification support device, verification support method, and computer product

A short cell multiplexer includes a sequence designating unit, in which reading intervals corresponding to QOS classes are set in respective reading interval setting registers. A counter memory is stored with the number of timings at which the short cells can be read. The sequence designating unit specifies the QOS class in which the number of timings reaches the reading interval on the basis of the reading interval and the number of timings, and gives to a reading unit an indication of reading the short cell belonging to this class.

Short cell multiplexer

A radar equipment of the present invention amplifies a reception signal with feedback based on the delay amount obtained from the correlation detection result. Accordingly, it becomes possible to maintain the reception signal (demodulated signal) level to a proper level depending on the distance to the target, and accurate measurement can be achieved with high precision. Namely, the reception signal is amplified depending on the distance to the target, and the reception signal level is made within a tolerable input level range of a logic circuit for performing correlation calculation. In particular, during tracking the target, even when a reflected signal is received with abrupt level variation caused by noise or a reflected signal from an object other than the target, incorrect detection of the target can be avoided by disabling the correlation calculation.

Radar equipment

A cell processing apparatus which executes processing for switching a short-packet in AAL Type 2 cell format has a separation processing unit and a restoration processing unit. The separation processing unit splits a short packet, which has a length greater than a length L (=48) bytes capable of being accommodated in one ATM cell, into two portions, accommodates significant data containing (1) one of the short-packet portions and (2) short-packet length information, in a payload area of the first ATM cell, accommodates remaining significant data including another short-packet portion, which could not be accommodated in the first ATM cell, in a payload area of the second ATM cell, and inputs the first and second ATM cells to an ATM switch. The restoration processing unit refers to the short-packet length information that has been accommodated in the first ATM cell output from the ATM switch, restores the original short packet, the length of which exceeds L bytes, using the short packet portions that have been accommodated in respective ones of the first and second ATM cells, and sends the restored short packet to a line in the AAL Type 2 cell format.

Cell processing apparatus, ATM exchange and cell discarding method

The quality classes of arriving short cells and the ATM virtual connections to be multiplexed are identified based on the CIDs of those short cells. Those short cells are written into FIFO memories corresponding to the ATM virtual connections and quality classes. A VC specification control section specifies one ATM virtual connection for each ATM cell sending timing. At this time, a sequence specification control section specifies one or more quality classes in sequence. A readout control section reads one or more short cells out from the FIFO memory in accordance with the specified ATM virtual connection and quality class, stores them in one ATM cell and sends the ATM cell to the ATM virtual connection specified by the VC specification control section.

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Kawasaki, Japan

Takayuki Sasaki