Seiko Epson Corporation

Takayuki Saiki

Kazuhiko Okawa

Hiroyuki Takamiya

Satoru Ito

Junichi Karasawa

Takashi Kumagai

Satoru Kodaira

Hisanobu Ishiyama

Kazuhiro Maekawa

Takashi Fujise

Shinya Sato

Masahiko Moriguchi

An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TCand TC, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads Pand Pfor electrically connecting the data lines and the output lines QLand QLof the data driver block are disposed. The control transistors TCand TCare disposed in the pad arrangement region.

Integrated circuit device and electronic instrument

A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.

Semiconductor device and method for manufacturing semiconductor device

An integrated circuit device includes first and second transistors NTrand PTrpush-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTrand PTrso that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTrand PTr

A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.

An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

Semiconductor device

An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.

Semiconductor device with electrostatic discharge protection

The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an element isolation region formed on the semiconductor substrate, a first impurity diffusion region that is formed in the semiconductor substrate and surrounds the element isolation region, a second impurity diffusion region that is formed in the semiconductor substrate, a first wiring electrode and a second wiring electrode that are electrically connected to the first impurity diffusion region on both sides of the element isolation region, an output terminal that outputs signals to outside, a wiring that electrically connects the first wiring electrode and the second wiring electrode to the output terminal, and a third wiring electrode and a fourth wiring electrode that are electrically connected to the second impurity diffusion region corresponding to the first and second wiring electrodes.

The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.

Semiconductor device for electrostatic protection

A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor. A fourth diffusion region which makes up a Schottky diode together with the silicide layer is further provided between the silicide layer and the third diffusion region.

Semiconductor device having electrostatic protection circuit and method of fabricating the same

A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact. An electrostatic charge injection through the pad and contact is discharged mainly through a first discharge path guided to a channel (P-type well) of the N-type MOS transistor through the second diffusion region (N-type), N-type well under the second element isolation region, and second diffusion region (N-type). A discharge path passing through the silicide layer rarely functions as a discharge path, since the contact resistance value between the silicide layer and first diffusion region is greater than the resistance value of the first diffusion region.

Growing community of inventors

Suwa, Japan

Takayuki Saiki