Kabushiki Kaisha Toshiba

Takayuki Otani

Yasumitsu Nozawa

Takashi Suzuki

Kenichi Nakamura

Makoto Segawa

Satoru Hoshi

A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, and a controlling integrated circuit which is provided in the memory system in the package, and when an instruction of data transfer within the memory system is received from exterior of the package, controls an execution of the data transfer to be executed within the memory system such that data of memory cells at addresses of a first memory integrated circuit are read out, and the readout data are written into memory cells at addresses of a second memory integrated circuit.

Multi-chip package type memory system

A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selection lines, and blown when a defect exists, a normal row non-selection circuit (inverters IN3 and IN6 and gate G3) when one of the fuses (F1 to F128) is blown, setting a corresponding normal row in a non-selected state, and a spare row selection circuit (gates G4, G5, and G6, transistors P2 and N1, a NOR gate NR1, and an inverter IN6) selecting the spare row instead of the defective normal row. The spare row selection circuit performs dynamic operation in synchronism with a clock (ck). In this manner, control of, when a defect exists in a normal row or column, switching the defective row or column to a spare row or column is performed by dynamic operation in synchronism with an internal clock, thereby increasing the access speed.

Semiconductor memory device

A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well bias voltage (V.sub.BP1) is applied to the first well (N-type) and a second well bias voltage (V.sub.BN1) is applied to the second well (P-type); a second circuit (201; 202) formed in a third well (N-type) and a fourth well (P-type) of the same semiconductor substrate as above, supplied with the first supply voltage (V.sub.ss) and a third supply voltage (V.sub.cc2) higher than the first supply voltage but different from the second supply voltage (V.sub.cc), and activated when a third well bias voltage (V.sub.BP2) is applied to the third well (N-type) and a fourth well bias voltage (V.sub.BN2) is applied to the fourth well (P-type); a first bias circuit (20) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the first well bias voltage (V.sub.BP1); a second bias circuit (21) supplied with the first and second supply voltages (V.sub.ss and V.sub.cc), for generating and outputting the second well bias voltage (V.sub.BN1); a third bias circuit (16) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the third well bias voltage (V.sub.BP2); and a fourth bias circuit (17) supplied with the first and third supply voltages (V.sub.ss and V.sub.cc2) for generating and outputting the fourth well bias voltage (V.sub.BN2). In the semiconductor device, even if any of the second supply voltage (V.sub.cc) and the third supply voltage (V.sub.cc2) is first supplied, it is possible to prevent the latch-up phenomenon caused by the floated substrate potential.

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Hachioji, Japan

Takayuki Otani