Texas Instruments Corporation

Takayuki Niuya

Hiroyuki Yoshida

Toshiyuki Nagata

Yoshihiro Ogata

Yoichi Miyai

Katsushi Boku

Boyang Lin

Song C Park

Yuji Iwasawa

A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.

Trench-type semiconductor memory device

A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film(54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

Method of forming a trench-type semiconductor memory device

A latch-type SRAM memory cell having a number of MOS transistors arranged to maintain symmetry with each other circuitwise, in which the source regions of the MOS transistors are arranged so as to be adjacent semiconductor regions of opposite conductivity with respect thereto. Zener diodes are formed between the adjacent source and semiconductor regions with each of these Zener diodes being connected between their respective source regions and a power supply. Since current to each source region of paired MOS transistors flows effectively to the power supply or ground side via a Zener diode using a tunneling effect, a rise in the source region potential can be reduced, and an increase in the transistor threshold value can be controlled. In this way, symmetry of the paired transistors can be maintained, and the performance of the memory cell, e.g., memory cell data retention ability and drive current ability, can be increased. In addition, a high degree of integration and miniaturization of the device can be achieved with the Zener diodes, and a large degree of tolerance can be obtained for fluctuations in silicification conditions and fluctuations in surface concentration of the source and drain regions, as well as for variations during contact formation. Because of this, it will be possible to produce good quality, highly integrated semiconductor devices at high yields.

Semiconductor device

A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell. Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

French-type semiconductor memory device with enhanced trench

A semiconductor device in which a bit line (41), which is adhered to a contact hole (49) between polysilicon gate electrodes (35) and (36), is directly connected with an SiO.sub.2 film (53) having the same pattern on the gate electrodes; wherein an Si.sub.3 N.sub.4 layer (56) is buried outside the contact areas between the gate electrodes to approximately the same height as the SiO.sub.2 layer (53). The interlayer insulating film of the conventional memory cells array unit is no longer required, and it is not necessary to form contact holes in the interlayer insulating film. As a result, even if the gaps between the gates are designed to be small, there will be no short-circuiting between the bit line and word lines due to mask shifting, etc., making it possible to offer a highly integrated, highly reliable device.

Method of fabricating random access memory device having sidewall

A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

Method of manufacturing a semiconductor device

A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

Semiconductor device and method of manufacturing the same

Substrate bias generating circuit for MIS semiconductor device comprising an oscillating circuit, a capacitor, an MOS transistor and a Schottky barrier diode. One end of the oscillating circuit is connected to a V.sub.ss terminal which provides a reference potential. The capacitor is connected at one end thereof to the other end of the oscillating circuit. The MOS transistor is connected between the V.sub.ss terminal and the other end of the capacitor, with the Schottky barrier diode being connected between a node located between the other end of the capacitor and the MOS transistor, and the substrate. The Schottky barrier diode is operated by the majority carrier, thereby enabling the majority charge to be directly pumped out of the substrate and into the terminal V.sub.ss through the Schottky barrier diode with stability without requiring an injection of the minority charge into the semiconductor substrate. The pumping of the charge out of the substrate is permitted by lowering the potential of the node through the oscillating circuit.

Growing community of inventors

Tsukuba, Japan

Takayuki Niuya