Texas Instruments Corporation

Takayuki Niuya

Ming Yang

Vikram N Doshi

Shigenari Ukita

Ming J Hwang

Boyang Lin

Hiroshi Ono

Song C Park

Hayato Deguchi

Andrew A Anderson

A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact regionat a surface of a semiconductor substrate. The transistor, with the exception of the contact region, is covered with a first materialand the first material and the contact region are then covered with a layer of a second material. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layerin the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layerover the first conductive layer, and forming a second conductive layerover the dielectric layer.

Method for forming a memory integrated circuit with bitlines over gates and capacitors over bitlines

An embodiment of the instant invention is a method of oxidizing a first feature (feature and/or feature of FIG. and feature of FIG. ) while leaving a second feature substantially unoxidized (features and of FIG. and features and of FIG. ), the method comprised of subjecting the first and second features to an oxygen-containing gas and a separate hydrogen-containing gas. Preferably, the oxygen-containing gas is comprised of gas selected from the group consisting of O , N O, CO , H O, and any combination thereof, and the hydrogen-containing gas is comprised of H . The first feature is, preferably, comprised of polycrystalline silicon, silicon oxide, or a dielectric material, and the second feature is, preferably, comprised of tungsten.

Selective oxidation for semiconductor device fabrication

A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region at a surface of a semiconductor substrate . The transistor, with the exception of the contact region, is covered with a first material and the first material and the contact region are then covered with a layer of a second material . The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer over the first conductive layer, and forming a second conductive layer over the dielectric layer.

Method for forming a memory integrated circuit

A structure and method for fabricating an integrate circuit crown structure for use in a DRAM cell on a substrate comprising a common source/drain region ( ) disposed within a substrate ( ), the common source/drain region ( ) connected to a bitline ( ), a gate oxide ( ) disposed over the common source/drain region ( ) and forming at least two wordline gates ( ), at least two storage node source/drains ( ) adjacent to said gates ( ) and contacted by storage node contacts ( ) and a storage node bowl ( ), the bowl being formed within adjacent supporting layers formed over said wordline gates wherein the storage node bowl ( ) is formed, and electrically isolated from, the bitline ( ) without being exposed to etching agents during its formation and without forming a wine glass stem structure and a crown extending from the top of the storage node bowl ( ), is disclosed.

Simple stack cell capacitor formation

A method of fabricating an integrated circuit, and an integrated circuit so fabricated, is disclosed. A silicon dioxide layer (,) that is doped with both boron and phosphorous, typically referred to as BPSG, is used as a planarizing layer in the integrated circuit structure, above which conductive structures (,) are disposed. A silicon nitride layer (,) is in place below the BPSG layer (,), and serves as a barrier to the diffusion of boron and phosphorous from the BPSG layer (,) during high temperature processes such as reflow and densification of the BPSG layer (,) itself. Contact openings (PC, BLC, CT) are etched through the BPSG layer (,) and the silicon nitride layer (,) using a two-step etch process. The first etch selectively etches silicon dioxide relative to silicon nitride, and thus stops on silicon nitride layer (,); besides serving as an etch stop, silicon nitride layer (,) protects underlying active regions (,) from damage that may be caused by ionized oxygen released during oxide etch. A brief nitride etch is then used to clear silicon nitride layer (,), without damaging comer locations (NC) of the sidewall structures (,).

Silicon nitride dopant diffusion barrier in integrated circuits

A method for fabricating a memory cell includes forming a first access line (,) for a storage node (,) and forming a second access line (,) operable to access the storage node (,) in connection with the first access line (,). The first access line (,) includes a first terminal (,) and a second terminal (,). The second access line (,) includes a conductive layer (,) connected to the first terminal (,) of the first access line (,). An opening (,) is formed in the second access line (,) for connection of the storage node (,) to the second terminal (,) of the first access line (,). A sidewall (,) is formed in the opening (,) to form a contact hole (,) insulated from the conductor (,) of the second access line (,). The storage node (,) is formed having a self-aligned contact (,) formed in the contact hole (,) and connected to the second terminal (,) of the first access line (,).

Method for fabricating a memory cell

A semiconductor device (,) includes gates (,), source/drain regions (,), and self-aligned contacts (,). Each self-aligned contact (,) includes a polysilicon layer (,) overlying the associated source/drain region (,). The polysilicon layer (,) may include different doped regions (,) in accordance with the design and function of the device (,).

Self-aligned contact structure and method

A semiconductor device (2) includes contact gate structures (28, 30) associated with contacts (82, 84) to source/drain regions (42, 44). Each contact (82, 84) includes a polysilicon layer (50) overlying the associated contact gate structure (28, 30) and source/drain region (42, 44). The polysilicon layer (50) may include different doped regions (52, 58) in accordance with the design and function of the device (2).

Contact gate structure and method

A technique for reducing active area encroachment (birdsbeak) by using a polysilicon hard mask combined with both wet and dry etch for the isolation nitride. This process forms a thinner layer of nitride adjacent the openings for oxide growth, which reduces stress at the silicon/nitride interface. The advantages include control over birdsbeak, reliable gate oxide quality, low junction leakage current, an improved active area, improved isolation, low peripheral junction leakage, and higher field transistor threshold voltage.

Birdsbeak encroachment using combination of wet and dry etch for

An integrated circuit includes a conductive structure (66) is formed with a top layer of silicon nitride (62) and silicon nitride (70) sidewalls on a semiconductor substrate. The layer of silicon nitride (70) covering the sidewalls of the conductive structure (66) intersect with the layer of silicon nitride on top of the conductive structure with a relatively square shoulder. A subsequently deposited conductor makes contact with the surface of the semiconductor substrate (56) without shorting to the conductive structure (66) on the semiconductor substrate.

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Plano, TX, United States of America

Takayuki Niuya