Panasonic Corporation

Matsushita Electrical Industrial Co., Ltd.

Takayuki Morishige

Akihiro Watabe

Eiji Miyagoshi

Noboru Mizuguchi

Yuichiro Aihara

In order to cope with format conversion of user data, the bit rate value and VBV (Video Buffering Verifier) buffer size value in a sequence header of an input code and the VBV delay value in a picture header of the input code are modified to obtain an intermediate code (to), and additional information () is generated for distinguishing GOP (Group of Pictures) user data () from the other main data. A VBV buffer simulation is performed using this additional information () to multiplex the GOP user data in a picture user data region to a data amount such that the operation does not fail, whereby an output code is generated.

Code conversion method and device thereof

A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration.

Access arbiter and arbitrable condition verification device

An image processing device having a plurality of cores which attains more efficient memory access than conventionally attained. In the image processing device employing pipeline processing, a memory access section executes data transfer between an operation section including a plurality of cores each performing operation for image processing and an external memory . The memory access section has an access schedule storage portion which stores types of data transfers per stage, and executes data transfer between the operation section and the external memory in accordance with the storage contents of the access schedule storage portion . A system control section sets the types of data transfers in the access schedule storage portion at a stage preceding the stage at which the data transfers are executed. This makes it possible to change the types of data transfers with stages flexibly and thus allows the memory access section to execute only necessary data transfers at each stage without the necessity of arbitration.

Growing community of inventors

Kyoto, Japan

Takayuki Morishige