Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Hitachi Engineering Ltd

Takayuki Morioka

Tadaaki Bandoh

Yoshihiro Miyazaki

Jushi Ide

Shinichiro Yamaguchi

Hidekazu Matsumoto

Soichi Takaya

Kenji Hirose

Hirokazu Kasashima

Atsuhiko Nishikawa

Hiroaki Nakanishi

Masakazu Okada

Hiroaki Fukumaru

Hideyuki Hara

Ryosei Hiraoka

Hirokazu Hirayama

Yukio Kawamoto

Ryoichi Takamatsu

Norihito Kanno

Kayo Takahashi

Shuji Ishikura

Toshihisa Oka

An apparatus and a method of screen display whereby either a plurality of screens or a plurality of windows on a single screen are displayed. On at least one screen or in at least one window, areas representing either the other screens or the other windows are displayed. When a pointer pointing to a given position either on that one screen or in that one window is used to select any one of these areas therein, the pointer is made to appear either on another screen or in another window corresponding to the selected area.

Apparatus and method for screen display

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Suspended instruction restart processing system based on a checkpoint

A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

Operation control apparatus for a processor having a plurality of

A microprogram controlled data processing apparatus executes multi-operand instructions in which one or more operand specifiers are provided for specifying the addressing for each operand independently from the operation code of the instruction. An instruction execution unit receives a top address of a microprogram from a decoding unit, a ready status signal and a signal from the decoding unit indicating whether a destination of an operand is in a general purpose register or in a memory unit, and writes an operand into a destination address of a register on the memory unit under control of a microprogram. Because the destination of the operand is indicated by the instruction decoding unit, it is not necessary to determine this information by microinstruction execution, with the result that execution of the instruction can be performed at high speed.

Microprogrammed control data processing apparatus in which operand

A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between adjacent layers of the hierarchy. The data processors are connected to a plurality of first layer serial bus loops and the I/O device which is commonly accessible by the data processors is connected to a second layer of serial bus loop. The interbus linkage devices control linkage among the plurality of serial bus loops and carry out routing control for a start command from the data processor to the I/O device, routing control for an interruption to report the end of I/O device operation, routing control for data transfer, routing control for a request interruption and exclusive use control of the shared I/O device.

Multi-computer system with plural serial bus loops

A printed circuit board loaded with an electronic circuit and constructed to be capable of being inserted in and withdrawn from a bus line on on-line status, in which the input to or the output from the printed circuit board is locked out in response to the presence of two conditions, one is the presence of a demand for insertion or withdrawal of the printed circuit board on on-line status and the other is the presence of such a condition that no information exchange is being made between the printed circuit board and other unit connected with the bus line, thereby releasing the electrical connection between the bus line and the printed circuit board so that the printed circuit board can now be inserted in or withdrawn from the bus line on on-line status.

Printed circuit board capable of being inserted and withdrawn on on-line

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Hitachi, Japan

Takayuki Morioka