Matsushita Electric Industrial Co., Ltd.

Takayuki Minemaru

Hisashi Takayama

Satoshi Takayama

Mizuki Segawa

Toshiki Yabu

Masahiro Yasumi

Kunitoshi Aono

Akihiko Ohtani

Mikio Fujiwara

Ichirou Matsuo

Mana Saishi

Tadashi Fukumoto

An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Semiconductor device with varying width electrode

A product P is calculated by multiplying a multiplicand X and a multiplier factor Y which are 16-bit fixed-point numbers and binary numbers in two's complement notation. Thus obtained product P is 31-bit length and the most significant bit thereof is a sign bit. Further, the product P is rounded down or rounded off to obtain a 16-bit rounded result PR. At this time, the 15-bit rounding data R to be added to the product P is changed according to the sign of the product P which is predicted so as to obtain respective rounded results which have the same absolute value from the two products which have different signs from each other and the same absolute value. In detail, in a case of rounding-down, '0000' and 'TFFF' (both in hexadecimal numeral) are respectively generated as the rounding data when the product P is positive and when the product P is negative. In a case of rounding-off, '4000' and '3FFF' (both in hexadecimal numeral) are respectively generated as the rounding data R when the product P is positive and when the product P is negative. The rounding data is added to the less significant 15 bits of the thus calculated product P and the less significant 15 bits of the thus added result are deleted to make the remaining 16 bits the rounded product PR.

Multiplication circuit having rounding function

Image data is processed to enlarge and contract an original image, represented by the data, by P times in an X-axis direction while the data is subjected to interpolation. The letter P denotes an arbitrary positive rational number. It is supposed that each of regions among pixels of the original image is divided into sub areas having a number of N by M, that is, N in the X-axis direction and M in a Y-axis direction. The letter N denotes an arbitrary integer equal to or greater than 2. The letter M denotes an arbitrary integer equal to or greater than 1. An N-time interpolation enlarging device or step serves to execute an interpolation process determined by an original-image sub area corresponding to a pixel of an enlargement/contraction-resultant image while simultaneously generating a plurality of pieces of process-resultant data representing a part of an image enlarged from the original image by N times in the X-axis direction. An arbitrary-magnification enlarging/contracting device or step serves to subject the plurality of the pieces of the process-resultant data to image enlargement and contraction at an arbitrary magnification in the X-axis direction without executing interpolation, and also serves to process the plurality of the pieces of the process-resultant data to enlarge and contract an image, represented by the plurality of the pieces of the process-resultant data, by P/N times in the X-axis direction.

Hybrid interpolation and non-interpolation method and apparatus for

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Osaka, Japan

Takayuki Minemaru