Denso Corporation

Takayuki Matsuda

Akimasa Niwa

Tsuyoshi Yamamoto

Hideaki Ishihara

Toshihiko Matsuoka

Masahiro Kamiya

Naoki Ito

A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address updated every time when each execution of instruction is completed, includes update ceasing means for ceasing the program address from being updated when an stopping time comes in order to abort a first task defined by a first computer program and overwriting means for overwriting the program address with an initial address of a second computer program when a predetermined time comes in order to start to execute a second task defined by the second computer program at the predetermined time.

Microprocessor starting to execute a computer program at a predetermined interval

A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Processor, microcomputer and method for controlling program of microcomputer

At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention of an instruction decode stage in accordance with a setting address outputted from an EXE/MA buffer to an address bus. Thus, at the next processing timing at which the header address of the interrupt processing routine is loaded, the loaded header address is set in the program counter and fetching of a header instruction of the interrupt processing routine so that the interrupt processing routine can be immediately started.

Pipeline processing device and interrupt processing method

A signal generator detects a stage in which a central processing unit (CPU) reads an interrupt vector number from an instruction controller based on an address on an address bus and generates an address of a ROM to which the CPU makes access subsequently. The generated address is defined as a pre-reading address and this pre-reading address is supplied to the ROM via a selector before the CPU starts accessing to the ROM. In this case, an output buffer is turned off. Thereafter, when the CPU starts accessing to the ROM, the selector is switched and the output buffer is simultaneously turned on so that the address on the address bus is supplied to the ROM.

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Kariya, Japan

Takayuki Matsuda