Tokyo Electron Limited

Takayuki Komiya

Shinji Nagashima

Shigeyoshi Kojima

Yumiko Kawano

Hiroki Ohno

Yoshihide Sato

A method for forming a film includes the steps of: placing an object to be processed into a processing container; and generating M(BH)gas by feeding Hgas as carrier gas into a raw material container in which solid M(BH)(where M is Zr or Hf) is accommodated to introduce a mixture gas of Hgas and M(BH)gas having a volume ratio of flow rates (H/M(BH)) of 2 or more into the processing container, and deposit a MBfilm (where M is Zr or Hf and x is 1.8 to 2.5) on the object using a thermal CVD.

Method for forming a film including Zr, Hf or the like, and method for manufacturing a semiconductor device using the same

Both of a first insulating film and a second insulating film are formed by a spin coating method. Accordingly, the formation of the first insulating film and the second insulating film can be performed in the same SOD processing system. Moreover, the aforesaid formation of both of the first insulating film and the second insulating film by the spin coating method can provide favorable low dielectric constant properties and good adhesion of the first insulating film and the second insulating film.

Insulating film forming method and insulating film forming apparatus

A method for forming a multilevel interconnection of a semiconductor device of the present invention includes the steps of forming a first wiring layer by depositing a metallic film containing aluminum on an insulating film of a substrate and patterning the metallic film, forming an interlayer insulating film on the entire surface of the substrate to cover the wiring layer from the upper side, forming a connection hole reaching to the first wiring layer at a predetermined position of the interlayer insulating film, selectively depositing aluminum onto an interior of the connection hole at a volume fraction of 100% or more by CVD to fill the interior of the connection hole, flattening the entire upper surface of the interlayer insulating film including the connection hole filled with aluminum by a polishing process, washing the entire surface flattened by the polishing process, and depositing the metallic film containing aluminum at a predetermined position of the upper surface of the flattened and washed interlayer insulating film and patterning the metallic film, thereby forming a second wiring layer connected to the first wiring layer through aluminum filled in the connection hole.

Method for forming multilevel interconnection of semiconductor device

A polishing treatment called CMP (chemical mechanical polishing) is utilized for filling a contact hole formed in a silicon oxide film with a metallic layer in a manufacturing process of a semiconductor device. After a CMP treatment, a target surface, on which the silicon oxide film and the metallic layer are exposed, is washed with a washing liquid so as to remove residues due to the CMP treatment. The washing liquid comprises a fluorine compound for providing an etchant for the silicon oxide film and the metallic layer, and a protective agent which can be adhered onto a surface of the metallic layer so as to form a protective film. The ratio between the fluorine compound and the protective agent is set such that etching rates of the silicon oxide film and the metallic layer to be effected by the washing liquid fall within ranges of from 0.5 nm/min to 5 nm/min and from 0.5 nm/min to 6 nm/min, respectively, and a ratio between these etching rates falls within a range of from '2:1' to '1:3'.

Growing community of inventors

Nirasaki, Japan

Takayuki Komiya