Yamaha Corporation

Nippon Gakki Seizo Kabushiki Kaisha

Takayuki Kohdaka

Toshiyuki Takahashi

Takashi Ogata

Katsuhiko Ishida

Kuniaki Morita

Juhro Hoshi

Mituhiro Homme

Masamitu Hirano

Masao Noro

Tatsuya Kishii

Tatuya Kishii

A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control. The CMOS gate is provided with an auxiliary PMOS transistor being inserted at the PMOS transistor side and an auxiliary NMOS transistor being inserted at the NMOS transistor side. A timing control circuit is provided that generates a control clock signal adapted to maintain the auxiliary PMOS transistor and the auxiliary NMOS transistor in an OFF state during a specified period of time during which an electric potential output of the CMOS gate varies.

Logic circuit controlled by a plurality of clock signals

The digital-to-analog conversion apparatus operates to convert an digital input into a corresponding analog output. A digital filter is provided for oversampling the digital input having a varying value represented in the form of multiple bits. A delta-sigma modulator operates to effect delta-sigma modulation of the oversampled digital input to reduce a number of the multiple bits for requantizing the oversampled digital input with a certain S/N ratio. A low-pass filter is provided for converting the requantized digital input into an analog output. A level detecting circuit is provided for detecting when the value of the digital input falls below a predetermined level. A shifting circuit is disposed upstream of the delta-sigma modulator and is responsive to the detected results for increasing the value of the digital input so as to improve the S/N ratio in the delta-sigma modulator. An attenuator is disposed downstream of the delta-sigma modulator and is responsive to the detected results for effecting decreasing compensation for the increased value of the digital input while substantially maintaining the improved S/N ratio so as to produce an analog output corresponding to the digital input.

Digital-to-analog converter with delta-sigma modulation

An analog-to-digital converter mainly comprises an analog-to-digital conversion unit which produces a digital output, as an equivalent of an analog input supplied thereto, by performing a successive approximation. Herein, an instantaneous value of the analog input is compared with a reference signal so as to determine the digit in each of the bits of the digital output. The analog-to-digital converter can further comprise an analog comparator, an analog amplifier and a digital attenuator in order to reduce an effect of the noise. The analog amplifier amplifies the analog input by a gain so as to produce an intermediate analog signal. The analog-to-digital conversion unit converts the intermediate analog signal into an intermediate digital signal. The digital attenuator attenuates the intermediate digital signal by an attenuation rate so as to produce the digital output. The attenuation rate is determined such that a product, obtained by multiplying the gain and attenuation rate together, is normally equal to a value `1`. The analog comparator evaluates the level of the analog input by comparing it with predetermined levels in turn. Thus, the analog comparator controls the gain of the analog amplifier in accordance with a result of the evaluation.

Analog-to-digital converter

The chopping type comparator is provided with a capacitor which receives at its one end two input signals to be compared with each other through first and second analog switches alternately switchable between a conductive state and a nonconductive state. A clocked inverter is connected at its input terminal to another end of the capacitor. The clocked inverter is changed to an inactive state when one of the first and second analog switches is made conductive. A third analog switch is coupled between the input and output terminals of the clocked inverter. The third analog switch is made conductive concurrently when said one of the first and second analog switches is made conductive.

Chopping type comparator with clocked inverter

The digital-to-analog conversion apparatus operates in synchronization with a system clock signal having a short period to oversample and delta-sigma-modulate a digital input to produce a requantized digital signal. The system clock signal is mixed with noise leaked back due to the oversampling and delta-sigma modulating operation. The system clock signal is frequency-divided by the rate of one-fourth or less to produce a divided clock signal having a long period and being free of the noise. The requantized digital signal is detected each long period, and is pulse-modulated according to the detected results to generate a pulse signal having the long period. This pulse signal is low-pass-filtered to produce an analog output having improved S/N ratio.

A chopper type comparator, for comparing a first analog input signal voltage and a second analog input signal voltage to each other, includes an input portion for inputting the first and second analog input signals, respectively, and selectively outputting the first and second analog input signals, and a comparison portion for providing a result of comparison of the first and second analog input signals. The comparison portion includes a capacitor connected to a selected output of the input means at one terminal of the capacitor, an inverter having an MOS FET and of which an input side thereof connected to the other terminal of the capacitor, a path connected in parallel between the input and an output of the inverter across a analog switch, a switch control portion for controlling an electrical connection state of the analog switch in response to selection of the output of the input portion, the analog switch having a suppressing portion for suppressing transmission of a voltage variation to the input side of the inverter from the output side thereof across the analog switch.

Chopper type comparator

A digital-to-analog converter converts digital data in the floating-point representation into an analog signal. The mantissa part of the digital data is first converted into a first analog signal by an R-2R resistor ladder network. The first analog signal thus obtained is directly supplied to another r-2r resistor ladder network to produce second analog signals whose values are 2.sup.-N (N=0, 1, 2, . . . ) magnifications of the first analog signal. And, one of the second analog signals is selectively outputted in accordance with the exponent part of the digital data. A data converter is also provided for converting digital data in the form of a fix-point number into floating point data.

Floating point digital to analog converter with bias to establish range

A parallel analog-to-digital converter having reference-voltage generating means dividing the fundamental reference voltage into exponential reference voltages according to an exponential scale, and further dividing each voltage between two consecutive exponential reference voltages into a plurality of individual reference voltages. As a result, the individual reference voltages have a nonlinear (exponential) characteristic that as the amplitude of an analog input voltage increases, the increment of the individual reference voltages becomes larger exponentially, thus greatly reducing the number of comparators.

Parallel analog-to-digital converter

A floating-point digital-to-analog converting system which includes a mantissa digital-to-analog converter (DAC) and an exponent DAC. Normally, the mantissa DAC has a digital-to-analog converting accuracy higher than that of the exponent DAC because of differences in their construction. Hence, as long as the accuracy of the mantissa DAC is greater than that of the exponent DAC, an analog mantissa output from the mantissa DAC is used as an analog output of the present system. On other other hand, once the accuracy of the mantissa DAC goes below that of the exponent DAC, data obtained by shifting digital input data is applied to the mantissa DAC. Then, the exponent DAC multiplies the analog mantissa by a weight corresponding to the digital exponent data included in the digital input data. Thus, an analog output is obtained from the exponent DAC.

Floating-point digital-to-analog converting system

A digital-to-analog converter (DAC) converts digital input data into an analog output signal with less harmonic distortion over an entire signal-level range. An exponent value detector detects from the digital input data the number of bits by which the digital input data is to be shifted to form a mantissa part thereof. A digital shifter shifts the digital input data in accordance with the output of the exponent value detector, and outputs the mantissa part which is then supplied to a mantissa-part DAC. The mantissa-part DAC comprises an R-2R resistor ladder network and outputs the result of DA conversion of the mantissa part to an exponent-part DAC. The exponent DAC shifts the output of the mantissa-part DAC by an amount determined by the output of the exponent value detector, and outputs the shifted signal as the analog output signal of this DAC. A control circuit is provided between the digital shifter and the mantissa-part DAC, which prevents, in accordance with the output of the exponent value detector, the least significant bits of the mantissa-part DAC from operatively functioning to thereby decrease the number of operable bits thereof when the magnitude of the digital input data is small.

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Hamamatsu, Japan

Takayuki Kohdaka