Sumco Corporation

Sumitomo Mitsubishi Silicon Corporation

Nec Corporation

Nippon Steel Sumitomo Metal Corporation

Takayuki Kihara

Yuki Nakano

Kazushige Takaishi

Shinsuke Sadamitsu

Yasuyuki Hashimoto

Ryoya Terakawa

Toshiaki Ono

Takashi Nakayama

Masataka Hourai

Naoyuki Wada

Yoshitaka Yoshimura

Nobumitsu Takase

Masaya Sakurai

Kazuaki Kozasa

Katsuhisa Sugimori

Yumi Hoshino

Koji Sueoka

Jiro Kajiwara

Tomoyuki Kabasawa

Katsutoshi Yamamoto

Hiroki Ota

Shota Ono

Tomohisa Shimizu

Shoji Nogami

Shinichi Toriyama

Masahiro Kiyosawa

A polishing head includes a first ring-shaped member having an opening; a plate-shaped member that closes the opening on an upper side of the first ring-shaped member; a membrane that closes the opening on a lower side of the first ring-shaped member; a back pad adhered to a lower surface of the membrane; and a second ring-shaped member located below the back pad and having an opening that holds a polishing target workpiece. A space formed by closing the opening of the first ring-shaped member by the plate-shaped member and the membrane includes: a central region; and an outer peripheral region partitioned from the central region by a partition, and an inner peripheral edge region of the second ring-shaped member is located vertically below an outer peripheral edge of the outer peripheral region. A polishing apparatus includes the polishing head, and is used in a method of manufacturing a semiconductor wafer.

Polishing head, polishing apparatus, and method of manufacturing semiconductor wafer

An information processing system () includes an account-opening task server () and an agent server (), wherein the server () includes a transmission unit () that transmits, to the server (), when storing personal information of a user in a personal information database (), first authentication information for logging in the server () with respect to the user and a processing unit () that executes, when receiving the first authentication information, processing of reading the user information of the user, and the server () includes an ID registration unit () that stores second authentication information for the user to log in to the server () in an ID storage unit () in association with the first authentication information and a login unit () that reads, when receiving the second authentication information, the first authentication information corresponding to the second authentication information from the ID storage unit () and logs in to the server ().

Information processing system, information processing method, and program

A polishing head of a wafer polishing apparatus is provided with: a membrane head that can independently control a center control pressure pressing a center portion of a wafer, and an outer periphery control pressure pressing an outer peripheral portion of the wafer; an outer ring integrated with the membrane head so as to configure the outer peripheral portion of the membrane head; and a contact type retainer ring provided outside the membrane head. The membrane head has a central pressure chamber of a single compartment structure that controls the center control pressure, and an outer peripheral pressure chamber that is provided above the central pressure chamber, and that controls the outer periphery control pressure. A position of a lower end of the outer ring reaches at least a position of an inner bottom surface of the central pressure chamber.

Polishing head, wafer polishing apparatus using the same, and wafer polishing method using the same

Provided is a susceptor, capable of preventing occurrence of scratches on the back surface of a wafer attributable to lift pins, and reducing unevenness of the in-surface temperature distribution of the wafer. A susceptor according to one embodiment of this disclosure has a susceptor main body and a plate-shaped member, and when a wafer is conveyed, the front surface of the plate-shaped member ascended by lift pins supports the central part of the back surface of the wafer by surface contact. A separation space between the plate-shaped member and the susceptor main body, in a state in which the plate-shaped member is placed on the recessed part, enters further into the central side of the plate-shaped member, in a direction from the front surface to the back surface of the susceptor.

Susceptor and epitaxial growth device

Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Epitaxial silicon wafer and production method thereof

This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.

Silicon wafer and method of manufacturing same

A tray for film formation by a CVD method includes a tray main body () and a supporting member () mounted on the tray main body () for supporting a silicon wafer (). The supporting member () has a holding portion (), on which the silicon wafer () is directly placed. The holding portion () has its lower surface () apart from a surface () of the tray main body that is opposed to and apart from the supported silicon wafer (), whereby the thickness distribution of an oxide film formed on the silicon wafer can be made uniform. The tray has a structure for reducing a contact area between the supporting member () and the tray main body (), with the holding portion () having a tilted surface with its inner circumferential side closer to the tray main body surface () that is opposed to the silicon wafer.

Tray for CVD and method for forming film using same

Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Provided is a method applicable to the production of silicon wafers having crystal orientation &#x3c;100&#x3e; or &#x3c;110&#x3e; and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.

Silocon wafer supporting method, heat treatment jig and heat-treated wafer

A high resistivity p type silicon wafer with a resistivity of 100 &#x3a9;cm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 &#x3bc;m from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.

High resistivity silicon wafer and method for fabricating the same

In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

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Tokyo, Japan

Takayuki Kihara