Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Device Engineering Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi-high-technologies Corporation

Centre National De La Recherche Scientifique

Hitachi Vlsi Engineering Corp.

Universite Paris-sud Xi

Takayuki Kawahara

Kiyoo Itoh

Riichiro Takemura

Takeshi Sakata

Goro Kitsukawa

Yoshiki Kawajiri

Masashi Horiguchi

Masakazu Aoki

Ryoichi Hori

Katsutaka Kimura

Kunio Uchiyama

Takao Watanabe

Shoji Kubono

Kenichi Osada

Hiroshi Sato

Tomonori Sekiguchi

Masanao Yamaoka

Yusuke Jyouno

Kenchi Ito

Keiichi Yoshida

Atsushi Nozoe

Hideaki Kurata

Nozomu Matsuzaki

Hiromasa Takahashi

Takesada Akiba

Hiroaki Kotani

Naoki Miyamoto

Satoshi Noda

Naoki Kobayashi

Kazushige Ayukawa

Kenzo Kurotsuchi

Kazuo Ono

Naoki Kitai

Toshinori Harada

Satoru Akiyama

Ryoichi Kurihara

Takashi Kobayashi

Kazumasa Yanagisawa

Yoshimitsu Yanagawa

Ken Yamaguchi

Shunichi Saeki

Yoshinori Takase

Yoshikazu Saito

Kunihiro Katayama

Yoshinobu Nakagome

Masaharu Kubo

Masayuki M Nakamura

Norikatsu Takaura

Ryuta Tsuchiya

Naoshi Itabashi

Michitaro Kanamitsu

Terumi Sawase

Takashi Ishigaki

Akihiko Satoh

Yuji Satou

Goro Kitukawa

Kazuhiko Kajigaya

Koichiro Ishibashi

Hiroyuki Mizuno

Hiroki Fujisawa

Masayuki Miyazaki

Kazuyoshi Oshima

Natsuki Yokoyama

Hitoshi Tanaka

Tsugio Takahashi

Fumio Arakawa

Akira Kotabe

Kanji Oishi

Yasushi Goto

Makoto Hanawa

Tatsuo Nakagawa

Tetsuro Matsumoto

Masanori Isoda

Takahiro Onai

Yasushi Kawase

Hiroshi Otori

Toshikazu Tachibana

Takahide Yokoi

Makiko Yoshida

Nobuaki Kohinata

Claude Chappert

Takamichi Muramatsu

Sonoko Migitaka

Syunichi Saeki

Takehiro Shimizu

Paul Crozat

Noriyuki Hamma

Hiromi Tukada

Mssashi Horiguchi

Thibault Devolder

Joo-von Kim

To a biomolecule measuring apparatus, a semiconductor sensor for detecting ions generated by a reaction between a biomolecular sample and a reagent is set. The semiconductor sensor has a plurality of cells which are arranged on a semiconductor substrate, and each of which detects ions, and a plurality of readout wires. Each of the plurality of cells has an ISFET which has a floating gate and which detects ions, a first MOSFET Mfor amplifying an output from the ISFET, and a second MOSFET Mwhich selectively transmits an output from the first MOSFET to a corresponding readout wire R. Each of the plurality of cells is provided with a third MOSFET Mwhich generates hot electrons in the ISFET and which injects a charge to the floating gate of the ISFET. Here, the second MOSFET and the third MOSFET are separately controlled.

Biomolecule measuring device

Provided is a biomolecule measuring device capable of effectively reducing measurement noise occurring when measuring a biomolecule sample using a semiconductor sensor. This biomolecule measuring device generates a trigger to react a sample with a reagent after starting to send the reagent onto the semiconductor sensor that detects ion concentration (see FIG.).

Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG.).

Biomolecule information analysis device

Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.

Semiconductor storage device and data processing method

There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other.

Magnetic memory, method of manufacturing the same, and method of driving the same

An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which '1' and '0' are programmed is shared by two arrays and a sense amplifier.

Semiconductor device with low voltage programming/erasing operations

Semiconductor device with low voltage programming/erasing operation

The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.

Semiconductor recording device

For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Semiconductor device

Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.

Semiconductor device with back-gate voltage control of a logic circuit

To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.

Semiconductor storage device

An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

Semiconductor integrated circuit device

An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.

Semiconductor memory device

Growing community of inventors

Higashiyamato, Japan

Takayuki Kawahara