Kabushiki Kaisha Toshiba

Takayuki Kawaguchi

Masami Masuda

Yasumitsu Nozawa

Satoru Hoshi

Shigeto Mizukami

Jin Kashiwagi

Kouji Nakao

A reference voltage generating circuit generates reference voltage and outputs the thus generated reference voltage from an output terminal thereof. A voltage generating circuit lowers external power supply voltage according to the reference voltage supplied from the reference voltage generating circuit to output internal power supply voltage from an output terminal thereof. A transistor has a current path connected between a terminal to which the external power supply voltage is supplied and the output terminal of the voltage generating circuit or between the terminal to which the external power supply voltage is supplied and the output terminal of the reference voltage generating circuit and a gate supplied with constant voltage and has negative threshold voltage.

Power supply voltage lowering circuit used in semiconductor device

An object of the present invention is to enlarge voltage amplitude of bit lines at a short time when reading out data from memory cells. A semiconductor memory device according to the present invention comprises an initialization circuit,constituted of a plurality of memory cells MC,, MC,-MCn, precharge transistors Q,and Q,, and an equalizing transistor Q,, and a load circuit constituted of load transistors Q,and Q,. When reading out data from the memory cells MC,-MCn, supply of electric charge to bit lines BLA and BLB by the load transistors Q,and Q,is temporarily interrupted. Because of this, it is possible to enlarge the voltage amplitude of the bit lines BLA and BLB from the power supply voltage VDD as compared with the case of always supplying the electric charge to the bit lines BLA and BLB from the power supply voltage VDD. Furthermore, the semiconductor memory device of the present invention interrupts the supply of the electric charge to the bit lines BLA and BLB during writing to the memory cells MC,-MCn. Because of this, it is possible to reduce the current consumption, thereby improving write margin.

Semiconductor memory device

A semiconductor device which enables quick and reliable adjustment of the address transition detection pulse width has an address transition detector (ATD) and n PMOS transistors connected in parallel to an output terminal, the PMOS transistors behaving as pull-up transistors for the ATD. The PMOS transistors are controlled by controlling outputs of n controllers which generate the outputs from a pulse-like waveform applied to an input terminal thereof, thus the size of the PMOS transistors are substantially changed.

Semiconductor device

A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

Semiconductor memory device having bit line equalizing means

In a data read circuit, for a semiconductor storage device, data of a memory cell (11) selected according to an address is inputted to a sense amplifier (22) via a pair of complementary first data lines (N1 to N6). The sense amplifier outputs the inputted and amplified data to a pair of complementary second data lines (N7, N8). First switching means (Tr3) equalizes the pair of complementary first data lines (N5, N6) at the input side of the sense amplifier (22) by making the first data lines conductive with respect to each other. Second switching means (Tr4) equalizes the pair of complementary second data lines (N7, N8) by making the second data lines conductive with respect to each other. Third switching means (Tr5, Tr6) equalizes by making the pair of first data lines (N5, N6) at the input side of the sense amplifier (22) and corresponding ones of the pair of second data lines (N7, N8) conductive with respect to each other. Second equalizing pulse generator means (42) generates a second equalizing pulse (.PHI..sub.eq ') when the address is changed, and turns on the first switch means (Tr3) by applying the second equalizing pulse to a control terminal of the first switch means. First equalizing pulse generator means (41) generates a first equalizing pulse (.PHI..sub.eq) when the address is changed, and turns on the second and third switching means (Tr4, Tr5, Tr6) by applying the second equalizing pulse to gate terminals of the second and third switching means. The load capacitance ]C(.PHI..sub.eq ')] connected to an output terminal of the second equalizing pulse generating means (42) is set smaller than the load capacitance [C(.PHI..sub.eq)] connected to an output terminal of the first equalizing pulse generator means (41). The number of stages of logical circuits constituting the second equalizing pulse generator means (42) is smaller than the number of stages of logical circuits constituting the first equalizing pulse generator means (41). Accordingly, with this data read circuit for a semiconductor storage device, the second equalizing pulse (.PHI..sub.eq ') from the second equalizing pulse generator means (42) is established earlier than the first equalizing pulse (.PHI..sub.eq) from the first equalizing pulse generator means (41).

Data read circuit for semiconductor storage device

This invention is a BiMOS logical circuit that provides a suitable output level with a limited number of components. The intermediate node of a PMOS transistor and an NMOS transistor is connected to the base of a bipolar transistor to control output voltage. The NMOS transistor is connected between the output terminal and the power source, and an output voltage approximately equal to the power supply voltage is obtained at the output terminal.

BiMOS logical circuit

The invention is a BiMOS logical circuit having a reduced number of components and increased operating speed. First and second MOS transistors are provided for, respectively, driving first and second bipolar transistors. The gates of these MOS transistors are, respectively, connected to the bases of the second and first bipolar transistors. The input terminal is connected to the gates of the MOS transistors.

Growing community of inventors

Yokohama, Japan

Takayuki Kawaguchi